82443MX Datasheet, PDF (16/173 Pages) Intel Corporation – PCIset

82443MX PCIset

One channel PC/PCI
 Real Time Clock

ACPI-compliant one-month alarm

256 bytes battery-backed RAM

AC’97 link controller (2 channels)
 Interface to AC’97 Audio CODEC
 Interface to modem CODEC

GPIO pins (31)

1 channel bus master IDE support ATA33

X-bus support
 SIO, KBC, and Flash are X-bus based

SMBus
 Host interface and slave interface

Power management functions
 ACPI 1.0 compliant power management
 ACPI arbiter disable
 PCI CLOCKRUN# and PME# support
 Static Clock Gating for AC’97 and USB
 Processor system bus power management
 Stop Grant and Halt special cycle translation from the host to the PCI bus
 Support for system Suspend/Resume via SUSCLK/SUS_STAT# (i.e., DRAM and Power-on
Suspend)
 SDRAM Self-Refresh power-down support via CKE pin in Suspend mode
 Independent, internal dynamic clock gating reduces the 440MX’s average power dissipation
 Static Stop Clock support
 Power-on Suspend mode
 Suspend-to-DRAM
 Suspend-to-Disk

System management
 SMI# generation
 SMRAM space remapping to A0000h (128 KB)
 Optional extended SMRAM space above 128MB, additional 128K/256K/512K/1MB TSEG from Top
of Memory, cacheable (cacheability controlled by the processor)

Signals/Packaging/Power
 416 signals
 492 mBGA
 3.3V core and mixed 3.3V with 5V tolerant and GTL I/O Buffers
 1.65 W TDP (typical) power dissipation with low power features enabled
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