82443MX Datasheet, PDF (158/173 Pages) Intel Corporation – PCIset

82443MX PCIset
SMBus
Host
Controller
SMBus Slave Interface
- Host Slave
- Shadow
P
smbus
Figure 26. 440MX SMBus Interfaces
To execute an SMBus host transaction, the type of transfer protocol, the address of SMBus device, the device
specific command, the data, and any control bits are first setup. Then the START bit is set, which causes the
host controller to execute the transaction. When the transaction completes, the 440MX generates an interrupt,
if enabled. The interrupt can be selected by IRQ9 or SMI#. The system software can wait for the interrupt to
signal completion or it can monitor the HOST_BUSY status bit. An interrupt is also signaled if an error
occurred during the transaction or if the transaction was terminated by the software setting the KILL bit. The
SMBHSTCNT, SMBHSTCMD, SMBHSTADD, SMBHSTDAT0, SMBHSTDAT1, and SMBBLKDAT Registers
should not be accessed after setting the START bit while the HOST_BUSY bit is active (until transaction
completion).
The SMBus controller does not respond to the START bit being set unless all interrupt status bits in the
SMBHSTSTS Register have been cleared.
For Block Read or Block Write protocols, the data is stored in a 32-byte block data storage array. This array is
addressed via an internal index pointer, which is initialized to zero on each read of the SMBHSTCNT Register.
After each access to the SMBBLKDAT Register, the index pointer is incremented by one. For Block Write
transactions, the data to be transferred is stored in this array and the byte count is stored in the
SMBHSTDAT0 Register prior to initiating the transaction. For Block Read transactions, the SMBus peripheral
determines the amount of data transferred. After the transaction completes, the byte count transferred is
located in SMBHSTDAT0 Register and data is stored in the block data storage array. Accesses to the array
during execution of the SMBus transaction always start at address 0.
Any register values needed for computation purposes should be saved prior to the starting of a new
transaction, as the SMBus host controller updates the registers while executing the new transaction.
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