82443MX Datasheet, PDF (37/173 Pages) Intel Corporation – PCIset

82443MX PCIset
GPIO Pins
Well
Input
Output/OD
Device Activity Default Function,
Monitor
Value
GPIO(30)
PGNT3#
Notes:
1. GPIO(x)* is capable of waking from Sleep states.
2. GPIO[0, 4, 9, 17, 18, 20] are capable of generating SCI and SMI like GPIO(1). These new GPIOs can generate resume
events.
3. The following GPIO registers: GPO_REG, GPIO_DIR and GPIO_CNTRL (Device #7, Function 3, PM I/O Space) are in
the Resume well and are reset by RSMRST# (unlike those which are not in the resume well and which are reset by
PCIRST#), and as a result retain their programming from S3-S5. They retain their values throughout and after Suspend
and are not reset to their default values.
The GPIO pin default priority is as follows :
1. All GPIO pins controlled by GPIO_CNTRL (Muxed GPIO Control Register, Device #7, Function 3, Power
Management System I/O space) always default to functional pins. These pins can be used as GPIOs if
the corresponding bit in the Muxed GPIO Control Register is 0. To use as a GPI or GPO the
corresponding GPIO_DIR bit must be set to the appropriate value.
2. The following four GPIO pins controlled by the GSCR Register (General Signal and Functional
Configuration Register - Device #7, Function 0) default to GPI/GPO:

REQA#

GNTA#

SERIRQ

IRQ8#
3. Priority between GPIO Control Registers (i.e., Muxed GPIO Control and GSCR Registers) and the GPIO
Direction Register (GPIO_DIR Register) is defined as follows: When a functional signal is selected via
these GPIO Control Registers the values programmed in the GPIO_DIR Register are ignored.
4. For the GPIO(14) pin with three functions (SPKR, FDD Device Monitor, GPIO), the priority is as follows:
It will be used as SPKR if GPIO_CNTRL Register (Muxed GPIO Control Register, Device #7, Function 3,
PM I/O space) bit 1 is programmed as 1. If the Muxed GPIO Control Register is programmed as 0, then
it is used as a an FDD Device monitor when the GPI_EN_DEV5 (Muxed GPIO Control Register, Device
#7, Function 3) bit is set. If both the Muxed GPIO Control Register bit 1 and GPI_EN_DEV5 are set to 0,
then the pin is used as a GPIO (GPIO_DIR Register programs it for either input or output).
5. The signals listed in Table 23 do not resume the system when used as GPIOs. They resume the system
when programmed as functional pins (i.e., PME#, LID, BATLOW#, EXSMI# or RI#).
6. GPIO(6)/IRQ8# is in the resume well but will not wake the system from the S3/S4/S5 states.
Table 23. System Resume with GPIO Signals Programmed as Functional Pins
GPIO
Functional Pin
GPIO(0)
PME#
GPIO(10)
LID
GPIO(11)
BATLOW#
25