82443MX Datasheet, PDF (56/173 Pages) Intel Corporation – PCIset

82443MX PCIset

PCI memory space from the Top of main Memory to 4 GB, which includes the following two specific
ranges:
 High BIOS area from 4 GB
 2 MB to 4 GB
6.2.2.1 Main DRAM Address Range (0010_0000h to Top of Main Memory)
The address range from 1 MB to the top of main memory is mapped to the main DRAM address range. All
accesses to addresses within this range will be forwarded to the main DRAM memory unless a hole in this
range is created using the fixed hole as controlled by the FDHC Register. Accesses within this hole are
forwarded to the external PCI bus.
The range of physical DRAM memory disabled by opening the hole is not remapped to the Top of Memory.
6.2.2.2 Extended SMRAM Address Range (Top of Main Memory - TSEG_SZ to Top of Main
Memory)
An extended SMRAM space of up to 1 MB can be defined in the address range just below the top of memory.
The size of the SMRAM space is determined by the TSEG_SZ value in the ESMRAMC Register. When the
extended SMRAM space is enabled, non-SMM processor accesses and all PCI-initiated accesses in this
range are terminated on the external PCI bus. When SMM is enabled the amount of memory available to the
system is equal to the amount of physical DRAM minus the value indicated by the TSEG_SZ bits.
6.2.2.3 PCI Memory Address Range (Top of Main Memory to 4 GB)
The address range from the top of main DRAM to 4 GB (top of physical memory space) is normally mapped
to the external PCI bus, with some exceptions mapped to the X-bus.
The two sub-ranges within the PCI Memory address range are defined as the High BIOS Address Range.
6.2.2.4 High BIOS Area (FFC0_0000h - FFFF_FFFFh)
The top 4 MB of the Extended Memory Region is reserved for System BIOS (High BIOS), extended BIOS for
PCI devices, and the A20 alias of the system BIOS. The processor begins execution from the High BIOS
after Reset. Except for the top 512 KB, which is always mapped to the X-bus, this region can be mapped to
either the X-bus or the external PCI bus. The upper subset of this region aliases to the 256 KB area just
below 16 MB. The actual address space required for the BIOS is less than 4 MB, but the minimum processor
MTRR range for this region is 2 MB, so the full 2 MB must be considered.
6.3 System Management Mode (SMM) Memory Range
Main memory can be used as System Management RAM (SMRAM) by enabling the System Management
Mode. Two SMRAM options are supported: Compatible SMRAM (C_SMRAM) and Extended SMRAM
(E_SMRAM). System Management RAM (SMRAM) space provides a memory area that is available for the
SMI handlers and code and data storage. This memory resource is normally hidden from the system OS so
that the processor has immediate access to this memory space upon entry to SMM. Only the processor can
access SMM space.
Three options for SMRAM locations are provided:

Below 1-MB option that supports compatible SMI handlers.
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