82443MX Datasheet, PDF (107/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.6.2.5.1 ADDRESS COMPATIBILITY MODE
Whenever the DMA is operating, addresses do not increment or decrement through the High and Low Page
Registers. This is compatible with the 82C37 and Page Register implementation used in the PC-AT. This
mode is set after CPURST# is valid.
7.6.2.5.2 SUMMARY OF DMA TRANSFER SIZES
Table 58 lists each of the DMA device transfer sizes. The column labeled "Current Byte/Word Count Register"
indicates that the register contents represent either the number of bytes to transfer or the number of 16-bit
words to transfer. The column labeled "Current Address Increment/Decrement" indicates the number added to
or taken from the Current Address Register after each DMA transfer cycle. The DMA Channel Mode Register
determines if the Current Address Register will be incremented or decremented.
DMA Device Date Size
and Word Count
8-Bit I/O, Count By Bytes
16-Bit I/O, Count By Words
(Address Shifted)
Table 58. DMA Transfer Size
Current Byte/Word
Count Register
Current Address
Increment/Decrement
Bytes
1
Words
1
7.6.2.5.3 ADDRESS SHIFTING WHEN PROGRAMMED FOR 16-BIT I/O COUNT BY WORDS
The 440MX maintains compatibility with the DMA implementation in the PC-AT, which used the 82C37. The
DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note that the least significant
bit of the Low Page Register is dropped in 16-bit shifted mode. When programming the Current Address
Register when the DMA channel is in this mode, the Current Address must be programmed to an even
address with the address value shifted right by one bit. Table 59 shows the address shifting for 16-bit I/O DMA
transfers.
Table 59. Address Shifting in 16-bit I/O DMA Transfers
Output
Address
8-Bit I/O Programmed
Address (Ch 0-3)
16-Bit I/O Programmed
Address (Ch 5-7)
(Shifted)
A0
A0
0
HA[16:1]
HA[16:1]
HA[15:0]
HA[23:17]
HA[23:17]
Note:
The least significant bit of the Page Register is dropped in 16-bit shifted mode.
HA[23:17]
7.6.2.5.4 AUTOINITIALIZE
By programming a bit in the DMA Channel Mode Register, a channel may be set up as an Autoinitialize
channel. When a channel undergoes autoinitialization, the original values of the Current Page, Current
Address and Current Byte/Word Count Registers are automatically restored from the Base Page, Address,
and Byte/Word Count Registers of that channel following TC. The Base Registers are loaded simultaneously
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