82443MX Datasheet, PDF (79/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Current CS# SRAS SCAS WE# Address
State
#
#
Command
Action
Notes
LH
L
H
BA,CA,A10 READ/READAP Start Read, optional AP 7
LH
L
L
BA,CA,A10 WRIT/WRITEAP New Write, optional AP
LL
H
H
BA,RA
ACT
ILLEGAL
2,10
LL
H
L
BA,A10
PRE/PALL
ILLEGAL
2,11
LL
L
H
X
CBR/SELF
ILLEGAL
11
LL
L
L
Opcode
MRS
ILLEGAL
11
Write
HX
X
X
X
DSEL
NOP
recovering L H
H
H
X
NOP
NOP
with auto L H
L
H
BA,CA,A10 READ/READAP ILLEGAL
2,7,10
precharge L H
L
L
BA,CA,A10 WRIT/WRITEAP ILLEGAL
2,10
LL
H
H
BA,RA
ACT
ILLEGAL
2,10
LL
H
L
BA,A10
PRE/PALL
ILLEGAL
2,11
LL
L
H
X
CBR/SELF
ILLEGAL
11
LL
L
L
Op Code MRS
ILLEGAL
11
Refreshing H X
X
X
X
DSEL
NOP
LH
H
H
X
NOP
NOP
LH
L
X
X
READ/ READAP ILLEGAL
11
LL
H
X
X
ACT/PRE/PALL ILLEGAL
11
LL
L
X
X
CBR/SELF/MRS ILLEGAL
11
Mode
HX
X
X
X
Register
DSEL
NOP-Enter idle after
tmrd
accessing L H
H
H
X
NOP
NOP-Enter idle after
tmrd
LH
L
X
X
READ/WRITE/ ILLEGAL
11
READAP/
WRITEAP
LL
X
X
X
ACT/PRE/PALL/ ILLEGAL
11
CBR/SELF/MRS
Notes:
Key: H: High Level, L: Low Level, X: don’t care, V: Valid data input, BA: Bank Address, AP: Auto Precharge, CA: Column
Address, RA: Row Address.
*All entries assume that CKE was active (high level) during the preceding clock cycle.
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