82443MX Datasheet, PDF (135/173 Pages) Intel Corporation – PCIset

82443MX PCIset

OCW2 is used to control the rotation of interrupt priorities when operating in the rotating priority mode
and to control the End of Interrupt (EOI) function of the controller.

OCW3 is used to set up reads of the ISR and IRR, to enable or disable the Special Mask Mode (SMM),
and to set up the interrupt controller in polled interrupt mode.
As shown in Figure 17, all ICWs must be programmed prior to programming the OCWs.
7.10.1.4 End-of-Interrupt Operation
7.10.1.4.1 END OF INTERRUPT (EOI)
The In Service (IS) bit can be set to 0 automatically following the trailing edge of the second INTA# pulse
(when AEOI bit in ICW1 is set to 1) or by a command word that must be issued to the Interrupt Controller
before returning from a service routine (EOI command). An EOI command must be issued twice with this
cascaded interrupt controller configuration, once for the master and once for the slave.
There are two forms of EOI commands: Specific and Non-Specific. When the Interrupt Controller is operated
in modes that preserve the fully nested structure, it can determine which IS bit to set to 0 on EOI. When a
Non-Specific EOI command is issued, the Interrupt Controller automatically sets to 0 the highest IS bit of
those that are set to 1, since in the fully nested mode the highest IS level was necessarily the last level
acknowledged and serviced. A non-specific EOI can be issued with OCW2 (EOI=1, SL=0, R=0).
When a mode is used that may disturb the fully nested structure, the Interrupt Controller may no longer be
able to determine the last level acknowledged. In this case, a Specific EOI must be issued which includes as
part of the command the IS level to be reset. A specific EOI can be issued with OCW2 (EOI=1, SL=1, R=0,
and LO-L2 is the binary level of the IS bit to be set to 0).
It should be noted that an IS bit that is masked by an IMR bit will not be cleared by a non-specific EOI if the
Interrupt Controller is in the Special Mask Mode.
7.10.1.4.2 AUTOMATIC END OF INTERRUPT (AEOI) MODE
If AEOI=1 in ICW4, then the Interrupt Controller operates in AEOI mode continuously until reprogrammed by
ICW4. Note that reprogramming ICW4 implies that ICW1, ICW2, and ICW3 must be reprogrammed first, in
sequence. In AEOI mode, the Interrupt Controller automatically performs a non-specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. Note that from a system standpoint, this mode should be
used only when a nested multi-level interrupt structure is not required within a single Interrupt Controller. The
AEOI mode can only be used in a master Interrupt Controller and not a slave (on CNTRL-1 but not CNTRL-2).
7.10.1.4.3FULLY NESTED MODE
The Fully Nested mode is entered after initialization unless another mode is programmed. The interrupt
requests are ordered in priority from 0 through 7 (0 being the highest). When an interrupt is acknowledged,
the highest priority request is determined and its vector placed on the bus. Additionally, a bit in the Interrupt
Service Register (IS[0:7]) is set. This IS bit remains set until the microprocessor issues an End of Interrupt
(EOI) command immediately before returning from the service routine. Or, if the AEOI (Automatic End of
Interrupt) bit is set, this IS bit remains set until the trailing edge of the second INTA#. While the IS bit is set, all
further interrupts of the same or lower priority are inhibited, while higher levels generate an interrupt (which is
acknowledged only if the microprocessor internal interrupt enable flip-flop has been re-enabled through
software).
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