82443MX Datasheet, PDF (32/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Signal
IOR#
IOW#
IRQ12
(Mouse IRQ)
IRQ8# /
GPIO(6)
IRQ[3:7]
IRQ1
(KBC IRQ)
KBCCS# /
Type
Description
I/O
I/O Read. IOR# is the command to an X-bus I/O slave device that the slave may
drive data on to the X-bus data bus (SD[15:0]). The I/O slave device must hold
the data valid until after IOR# is negated. IOR# is driven high upon PCIRST#.
During Reset:
After Reset:
During POS:
High-Z
High
High
I/O
I/O Write. IOW# is the command to an X-bus I/O slave device that the slave
may latch data from the X-bus data bus (SD[7:0]). IOW# is driven high upon
PCIRST#.
During Reset:
After Reset:
During POS:
High-Z
High
High
I
Interrupt Request 12/ Mouse Interrupt. This pin provides a mouse interrupt
function. Config Dev #7, offset 4e :bit 4 in the X-bus Chip Select Register
determines the functionality of IRQ12. When bit 4=0, the standard interrupt
function is provided and this pin can be tied to the X-bus connector. When bit
4=1, the mouse interrupt function is provided and this pin can be tied to the
IRQ12 output of the keyboard controller.
When the mouse interrupt function is selected, a low-to-high transition on this
signal is latched by the 440MX and an INT is generated to the processor as
IRQ12. An internal IRQ12 interrupt will continue to be generated until a Reset or
an I/O read access to address 60h (falling edge of IOR#) is detected. After Reset,
this pin provides the standard IRQ12 function (as an input).
I / I/O
IRQ8# is always an active low edge-triggered interrupt input (i.e., this interrupt
cannot be modified by software). Upon PCIRST#, IRQ8# is placed in active-low
edge-sensitive mode. This signal is muxed with GPIO(6).
During Reset:
After Reset:
During Powerdown:
High-Z
High-Z
High-Z
I
Interrupt Requests [3:7]. The IRQ signals provide both system board
components and X-bus I/O devices with a mechanism for asynchronously
interrupting the processor. The assertion mode of these inputs depends on the
programming of the two ELCR Registers. When an ELCR bit is programmed to a
0, a low-to-high transition on the corresponding IRQ line is recognized as an
interrupt request. This "edge-triggered" mode is the 440MX default. When an
ELCR bit is programmed to a 1, a high level on the corresponding IRQ line is
recognized as an interrupt request. This mode is "level-triggered" mode.
I
Keyboard Interrupt. This is the interrupt from the keyboard controller. An
internal flip-flop is placed between the pin and the 8259 to be compatible with
keyboard controllers which only pulse IRQ1 to signal an interrupt. A low-to-high
transition on IRQ1 can be latched by the 440MX. Reads to port 60h clear the
internal flip flop, at which time the flip-flop is armed for another low-to-high
transition.
O / I/O Keyboard Chip Select. KBCCS# is asserted during I/O Read or Write accesses
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