82443MX Datasheet, PDF (48/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Signal
HA[15]#
HA[7]#
MA12#
MA11#
MA10
MA8#
Table 27. Power-Up Options During Reset
Register
Name/Bit
Description
None
Quick Start Select. The value on HA[15]# sampled at the rising edge of
CPURST# reflects whether the Quick Start Stop Clock mode is enabled in the
processor.
None
In-order Queue Depth Status. The value on HA[7]# sampled at the rising
edge of CPURST# reflects whether the IOQD is set to 1 or the maximum
allowable by the processor bus. If the maximum processor bus In-order Queue
depth is selected, the 440MX will throttle it to 4 by asserting BNR# appropriately
as per the processor bus protocol.
NBXCFG[13] Reserved. Strap to a ‘1’ internally.
NBXCFG[2]
In-Order Queue Depth Enable. If MA11# is strapped to ‘0’ during the rising
edge of PCIRST#, then the 440MX will drive HA[7]# low during the CPURST#
de-assertion. This forces the processor bus to be configured for non-pipelined
operation. If MA11# is strapped to ‘1’ (default), then the 440MX does not drive
HA[7]# low during Reset, and if HA[7]# is sampled in default non-driven state
(i.e., pulled up as far as GTL+ termination is concerned) then the maximum
allowable queue depth by the processor bus protocol is selected (i.e., 8).
Note that in this case external logic supplied by the OEM can be used to drive
HA[7]# and select the proper mode. If the maximum theoretical queue depth
(i.e., 8) is selected by keeping HA[7]# de-asserted during Reset, the 440MX
uses the BNR# mechanism to throttle the processor bus to a maximum of four
pipelined transactions.
MA[11]# IOQD
0
1
1
max.
PMCR[3]
Quick Start Select. The value on this pin at Reset determines which stop clock
mode is used. If MA10 = 1 during the rising edge of PCIRST#, then the 440MX
drives HA[15]# low during CPURST# de-assertion. This configures the
processor for Quick Start mode.
Note: The default mode should be the active state of the signal used for
strapping. This sets the processor for Quick Start mode and the 440MX drives
HA[15]# low during CPURST# de-assertion. This signal is internally tied to a 50
Kohm pullup.
None
HOST_HFV (High Frequency VCO). An internal pulldown (a minimum of 50
Kohms) is used to select HOST_HFV to a ‘0’ as a default, indicating the Host
PLL is set to the slower VCO speed.
An external pullup may be used if a later decision is made to select the fast
Host PLL speed.
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