82443MX Datasheet, PDF (153/173 Pages) Intel Corporation – PCIset

82443MX PCIset
fetched from the table. The controller then begins transferring data to or from that PRD’s memory
region.
6. The IDE device signals an interrupt once its programmed data count has been transferred. The IDE
device also negates its DMA request signal, causing the 440MX to stop transferring data. If the 440MX
has also transferred the final data from the last PRD memory region, it will reset the BMIDEA bit in the
Status Register and mask the DMA request signal from the drive.
7. In response to the interrupt, the software resets the Start/Stop bit in the Command Register. It then
reads the controller status followed by the drive status to determine if the transfer completed
successfully.
7.12.6 “ULTRA DMA/33” SYNCHRONOUS DMA OPERATION
Ultra DMA/33 is a physical protocol used to transfer data between an Ultra DMA/33 capable IDE controller
such as the 440MX and one or more Ultra DMA/33 capable IDE devices. It utilizes the standard Bus Master
IDE functionality and interface to initiate and control the transfers. Ultra DMA/33 utilizes a “source
synchronous” signaling protocol to transfer data at rates up to 33 Mbytes/second. The Ultra DMA/33 definition
also incorporates a Cyclic Redundancy Checking (CRC-16) error checking protocol. CRC-16 only has the
ability for detecting errors, not correcting them.
7.12.6.1 Signal Descriptions
Table 78 lists the IDE signals that are redefined for Sync DMA protocol implementation.
Standard IDE
Signal Definition
PDIOW#
PDIOR#
PIORDY
Table 78. Ultra DMA/33 Control Signal Redefinition
Ultra DMA/33 Read
Cycle Definition
Ultra DMA/33 Write
Cycle Definition
440MX
ChannelSignal
STOP
STOP
PDIOW#
DMARDY#
STROBE
PDIOR#
STROBE
DMARDY#
PIORDY
PDIOW# is redefined as STOP for both read and write transfers. This is always driven by the 440MX and is
used to request that a transfer be stopped or as an acknowledgment to stop a request from an IDE device.
PDIOR# is redefined as DMARDY# for transferring data from the IDE device to the 440MX (read). It is used
by the 440MX to signal when it is ready to transfer data and to add wait states to the current transaction.
PDIOR# is redefined as STROBE for transferring data from the 440MX to the IDE device (write). It is the data
strobe signal driven by 440MX on which data is transferred during each rising and falling edge transition.
The PIORDY signal is redefined as STROBE for transferring data from the IDE device to the 440MX (read). It
is the data strobe signal driven by the IDE device on which data is transferred during each rising and falling
edge transition. PIORDY is redefined as DMARDY# for transferring data form the 440MX to the IDE device
(write). It is used by the IDE device to signal when it is ready to transfer data and to add wait states to the
current transaction.
All other signals on the IDE connector retain their functional definitions during Ultra DMA/33 operation.
141