82443MX Datasheet, PDF (115/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Table 64. 8237 Registers and DDMA Function
Register
Algorithm
Base Address
Since each DMA channel has a separate X-bus address for the Base Address
Register, the 440MX must perform one 16-bit write cycle via PCI. The data value
originally written by the CPU is written to the peripheral.
For DMA Channels 0-3, the 8237 Base Address Registers are mapped to ISA 0000h,
0002h, 0004h, and 0006h. For DMA Channels 5-7, the 8237 Base Address Registers
are mapped to ISA 00C4h, 00C8h, and 00CCh. Channel 4 is always assumed to be
inside the 440MX.
Since the 8237 does not permit read accesses to the Base Address Registers the
DDMA does not need to permit them.
For power-management purposes, the 440MX permits reading these registers via the
Alt Access Mode.
Base Word Count
Since each DMA channel has a separate X-bus address for the Base Word Count
Register, the 440MX must perform one 16-bit write cycle via PCI. The data value
originally written by the CPU is written to the peripheral.
For DMA Channels 0-3, the 8237 Base Word Count Registers are mapped to ISA
0001h, 0003h, 0005h, and 0007h. For DMA Channels 5-7, the 8237 Base Word Count
Registers are mapped to ISA 00C6h, 00CAh, and 00CEh. Channel 4 is always
assumed to be inside the 440MX.
Since the 8237 does not permit read accesses to the Base Word Count Registers, the
DDMA does not need to permit them.
For power-management purposes, the 440MX permits reading these registers via the
Alt Access Mode.
Page
Since each DMA channel has a separate X-bus address for the Page Register, the
440MX must perform one 16-bit read or write cycle via PCI. The data value originally
written by the CPU is written to the peripheral.
For DMA Channels 0-3, the 8237 Page Registers are mapped to ISA 0087h, 0083h,
0081h, and 0082h. For DMA Channels 5-7, the 8237 Page Registers are mapped to
ISA 008Bh, 0089h, and 008Ah. Channel 4 is always assumed to be inside the 440MX.
Current Address
Since each DMA channel has a separate X-Bus address for the Current Address
Register, the 440MX performs one 16-bit read cycle via PCI.
For DMA Channels 0-3, the 8237 Current Address Registers are mapped to ISA
0000h, 0002h, 0004h, and 0006h. For DMA Channels 5-7, the 8237 Current Address
Registers are mapped to 00C4, 00C8, and 00CCh.
Current Word Count Since each DMA channel has a separate ISA address for the Current Address
Register, the 440MX performs one 16-bit read cycle via PCI.
For DMA Channels 0-3, the 8237 Current Word Count Registers are mapped to ISA
0001h, 0003h, 0005h, and 0007h. For DMA Channels 5-7, the 8237 Current Word
Count Registers are mapped to 00C6, 00CA, and 00Ceh.
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