82443MX Datasheet, PDF (22/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Signal
NMI
RCIN#
RS(2:0)#
SMI#
STPCLK#
Type
Description
OD Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the
processor. The 440MX can generate an NMI when either SERR# or IOCHK# is
asserted. The processor detects an NMI on a rising edge. NMI is reset by
setting the corresponding NMI source enable/disable bit in the NMI Status and
Control Register.
I
Keyboard Controller Reset processor. This pin from the keyboard controller
saves the external OR gate needed. This is called RESET processor, because it
uses the KBC terminology. However, the signal is mainly used to generate INIT#.
I/O
Response. Indicates type of response according to the following:
RS[2:0]
000
001
010
011
100
101
110
111
Response Type
Idle state
Retry response
Deferred response
Reserved (Not driven by the 440MX)
Hard failure (Not driven by the 440MX)
No data response
Implicit writeback
Normal data response
OD System Management Interrupt. SMI# is an active low output synchronous to
PCICLK that is asserted by the 440MX in response to one of many enabled
hardware or software events.
Note: The 440MX allows synchronous SMI events to generate SMI# even after
STPCLK# has occurred.
OD Stop Clock Request. STPCLK# is an active low synchronous output
synchronous to PCICLK that is asserted by the 440MX in response to one of
many hardware or software events. When the processor samples STPCLK#
asserted, it responds by stopping its internal clock.
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