82443MX Datasheet, PDF (114/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.7.4.3 Read/Write Cycle Protocols
For read cycles on the PCI bus that correspond to distributed DMA channels, the 440MX performs the
following algorithm:
1. The 440MX issues a PCI retry to terminate this cycle.
2. The 440MX requests the PCI bus. Upon being granted access to the bus, the 440MX performs one or
more read cycles to the 8237 and/or the peripherals. The I/O location of the read cycle is calculated
based on several parameters: the DDMA Base Pointer Registers in the PCI Configuration space, the
DMA channel number (0-3, 5-7), and the register location (0h-Fh).
3. The 440MX uses the data obtained via the read cycles (along with the value in the 8237) to construct the
proper data value.
4. When the CPU retries the cycle, the 440MX responds with the proper data value.
For write cycles on the PCI bus that correspond to distributed DMA channels, the 440MX performs the
following algorithm:
1. The 440MX issues a PCI retry to terminate this cycle.
2. The 440MX requests the PCI bus. Upon being granted access to the bus, the 440MX performs one or
more write cycles to the 8237 and/or the peripherals. The I/O location of the write cycle is calculated
based on several parameters: the DDMA Base Pointer Registers in the PCI Configuration space, the
DMA channel number (0-3, 5-7), and the register location (0h-Fh).
3. The 440MX uses the data obtained via the CPU's original write cycles to determine the proper values to
write to the peripherals and to the 8237.
4. When the CPU retries the cycle, the 440MX allows it to complete normally.
Table 64 specifies the number of read cycles (and merging format) and the number of write cycles (and data
format) for each of the 8237 registers.
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