82443MX Datasheet, PDF (35/173 Pages) Intel Corporation – PCIset

82443MX PCIset
VTT[B:A]
Name
VCCRTC
GTL+ termination voltage used for early clamps.
Table 18. RTC Power Pins
Description
Power for RTC Well. 2.0V-3.3V. This power is not expected to be shut off unless
the RTC battery is removed or drained, or unless an external RTC is used.
Table 19. USB Power Pins
Name
Description
VCCUSB
Power for USB Logic. 3.3V. This power will not be shut off in low-power states
except for Mechanical Off.
VSSUSB
Ground for USB.
Note: VCCSUS and VCCUSB should both be on simultaneously.
Table 20. Resume Power Pins
Name
Description
VCCSUS
3.3V for Resume Well. This power is not expected to be shut off unless the
system is unplugged or the main battery is completely drained for a mobile
system.
Note: VCCSUS and VCCUSB should both be on simultaneously.
Table 21. VREF Power Pins
Name
Description
REFVCC
Reference for 5V tolerance on inputs. This power is shut off in some low-power
states.
4.2 GPIO Definition
The 440MX includes 31 GPIOs, twelve of which are located in the Resume Well.
The GPIOs located in the resume well have their reset control changed from PCIRST# to RSMRST#, and as
a result retain their programming from S3-S5. They retain their values throughout and after Suspend and are
not reset to their default values. The Well column in Table 22 lists all GPIOs in the resume well that are
affected by this change.
GPIO Pins
GPIO(0)*
GPIO(1)*
Table 22. GPIO Pins Programmed through Config. Dev.7, Fn. 0
Well
Input
Output/OD
Device Activity Default Function,
Monitor
Value
Resume PME#
PME#, 1
Resume GPI(1)
GPIO(1)
23