82443MX Datasheet, PDF (27/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Signal
PLOCK#
PME# /
GPIO(0)
PREQ[3]# /
GPIO(29)
PREQ[2:0]#
REQA# /
GPIO(2)
SERR#
STOP#
TRDY#
Type
Description
PIRQC# and PIRQD# are multiplexed with GPIO.
I/O
PCI Lock. Indicates an exclusive bus operation and may require multiple
transactions to complete. The 440MX asserts PLOCK# when it is doing non-
exclusive transactions on PCI. PLOCK# is ignored when PCI masters are
granted the bus.
I / I/O PCI Power Management Event. Driven by PCI peripherals to wake the system
from low-power states S1-S5. Now included in the PCI specification.
I/O
PCI Requests. 4 channels of bus master on the PCI bus.
I
I/OD
I/O
I/O
PC/PCI DMA Request. See Section 7.7 for a description.
If the PC/PCI request is not needed, this signal can be used as a GPIO.
System Error. SERR# can be pulsed active by any PCI device that detects a
system error condition. Upon sampling SERR# active, the 440MX can be
programmed to generate an NMI, SMI#, or interrupt. Some internal conditions
can also cause the 440MX to drive SERR# active.
Stop. STOP# indicates that the 440MX, as a Target, is requesting an initiator to
stop the current transaction. As an Initiator, STOP# causes the 440MX to stop
the current transaction. STOP# is an output when the 440MX is a Target and an
input when the 440MX is an Initiator. STOP# is three-stated from the leading
edge of PCIRST#. STOP# remains three-stated until driven by the 440MX as a
slave.
Target Ready. TRDY# indicates the 440MX's ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. A data
phase is completed when both TRDY# and IRDY# are sampled asserted. During
a read, TRDY# indicates that the 440MX, as a Target, has placed valid data on
AD[31:0]. During a write, it indicates the 440MX, as a Target is prepared to latch
data. TRDY# is an input to the 440MX when the 440MX is the Initiator and an
output when the 440MX is a Target. TRDY# is three-stated from the leading edge
of PCIRST#. TRDY# remains three-stated by the 440MX until driven as a target.
Signal
AC_BIT_CLK
AC_RST#
AC_SDATA_
IN(0)
AC_SDATA_
IN(1)
Table 7. AC’97 Signal Description
Type
Description
I
AC’97 Bit Clock. 12.288 MHz serial data clock
O
AC’97 Reset. Master H/W Reset
I
AC’97 Serial Data In. Serial TDM data input
I
AC’97 Serial Data In. Serial TDM data input
15