82443MX Datasheet, PDF (47/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Name
During Before
Cold Reset Reset
After State Isolate to Pu/pd
Reset During ‘H’ in
POS/STR Suspend
Notes
PCICLK Pulldown
—
—
—
(input) enabled
—
Int pd Weak pulldown keeps clk
100K low in STR (when synth.
May be powered down)
while leaks very little current
in POS. Resistor is disabled
in Normal operation.
Also connected during cold
Reset.
PCIRST# Pulldown Pulldown —
—
enabled
enabled
Notes:
1. All miscellaneous signals are CMOS buffers.
—
Int pd Internal pulldown is
100K connected during Suspend
and cold Reset.
5V Tolerance:
Although the 440MX never drives an output above 3.3V, many of the I/O buffers and input buffers can tolerate
external signals driven up to 5V. The following signals must be 5V tolerant:

All PCI inputs and I/Os

Al IDE inputs and I/Os

SERIRQ

IRQ14
Signals located in the Resume well are 3.3V tolerant only.
4.6 Power-Up/Reset Strap Options
Table 27 lists all power-up options that are loaded into the 440MX during system Reset. The 440MX is
required to float all signals connected to straps during system Reset (PCIRST# active) and keep them floated
for a minimum of four host clocks after the end of a Reset sequence. The first column lists the signal that is
sampled to obtain the strapping option. The second column shows the register into which the strapping option
is loaded. The third column describes the functionality that the strapping selects. Note that all signals used to
select power-up strap options are connected to either internal pull-down or pull-up resistors of approximately
50 Kohms. That selects a default mode on the signal during Reset. To enable different modes, external
pullups or pulldowns of approximately 10K ohms can be connected to particular signals. These pull-up or pull-
down resistors should be connected to the 3.3V power supply. The GTL+ signals are connected to the VTT
through the normal pullups. Processor bus straps controlled by the 440MX (e.g., A7# and A15#), are driven
active at least six clocks prior to the active-to-inactive edge of CPURST# and driven inactive four clocks after
the active-to-inactive edge of the CPURST#.
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