82443MX Datasheet, PDF (19/173 Pages) Intel Corporation – PCIset

82443MX PCIset
4.
SIGNAL DESCRIPTION AND PIN STATES
4.1 Pin List
This section provides a detailed description of the 440MX signals. The signals are arranged in functional
groups according to their associated interface. Table 2 through Table 15 provide pin descriptions for each
signal. The state of each 440MX signal during Reset is provided in the Power-Up State Initial Value section
(Section 0).
Some signals, i.e., HCLKIN, CPU Sideband signals are voltage dependent on the CPU clock interface. For
mobile Celeron processors, it is 2.5V.
Note that the processor address and data bus signals are logically inverted. In other words, the actual values
are inverted of what appears on the processor bus. All processor control signals follow normal convention. A
“0 ” indicates an active level (low voltage) if the signal is followed by the # symbol and a “1 ” indicates an
active level (high voltage) if the signal has no # suffix.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal
is at a low voltage level. When “#” does not follow the signal name the signal is asserted at the high voltage
level.
The following notations are used to describe the signal type:
I
Input pin
O
Output pin
OD
Open Drain Output pin. This pin requires a pullup to the VCC of the processor core.
I/OD Input / Open Drain Output pin. This pin requires a pullup to the VCC of the processor core.
I/O
Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal:
GTL+ Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details.
PCI
PCI bus interface signals. These signals are compliant with the PCI 5.0V Signaling
Environment DC and AC Specifications.
CMOS The CMOS buffers are Low Voltage TTL compatible signals. These are 3.3V only.
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