82443MX Datasheet, PDF (101/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.6 DMA Controller
7.6.1 REGISTER DESCRIPTION
The 440MX contains DMA circuitry that incorporates the functionality of two 82C37 DMA controllers (DMA-1
and DMA-2). The DMA registers control the operation of the DMA controllers and are all accessible from the
Host CPU via the PCI bus interface.
7.6.2 FUNCTIONAL DESCRIPTION
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven independently
programmable channels (Channels 0-3 and Channels 5-7). DMA Channel 4 is used to cascade the two
controllers and defaults to cascade mode in the DMA Channel Mode (DCM) Register. In addition to accepting
requests from DMA slaves, the DMA controller also responds to requests that are initiated by software.
Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1.
The DMA controller for Channels 0-3 is referred to as "DMA-1" and the controller for Channels 4-7 is referred
to as "DMA-2."
Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired
to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted)
transfers. The 440MX provides the timing control and data size translation necessary for the DMA transfer
between the memory (DRAM) and the X-bus I/O. ISA-compatible timing is supported.
The 440MX provides 24-bit addressing in compliance with the ISA-compatible specification. Each channel
includes a 16-bit ISA-compatible Current Register which holds the 16 least-significant bits of the 24-bit
address, an ISA-compatible Page Register that contains the eight next most significant bits of address.
The DMA controller also features an auto-initialization following a DMA termination.
At any time, the 440MX controller is either in master mode or slave mode. In master mode, the DMA controller
services a DMA slave request for DMA cycles. ISA masters are not supported. In slave mode, the 440MX
monitors both the X-bus and the PCI bus, decoding and responding to I/O read and write commands that
address its registers.
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