82443MX Datasheet, PDF (34/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Signal
Type
Description
SD[7:0]
I/O
System Data Bus. SD[7:0] provide the 8-bit data path for devices residing on the
X-bus. The 440MX three-states SD[7:0] during PCIRST#.
SYSCLK
O
X-Bus System Clock. SYSCLK is the reference clock for the X-bus. It drives the
X-bus directly. The SYSCLK is generated by dividing PCICLK by four.
During Reset:
After Reset:
During POS:
Running
Running
Low
NOTE: This clock is needed for external IR.
TC
O
Terminal Count. The 440MX asserts TC to DMA slaves as a terminal count
indicator. The 440MX asserts TC after a new address has been output, if the
byte count expires with that transfer.
When all the DMA channels are not in use, TC is negated (low). Upon PCIRST#,
TC is inactive.
During Reset:
After Reset:
During POS:
High
Low
High
ZEROWS#
I
Zero Wait States. An ISA slave asserts ZEROWS# after its address and
command signals have been decoded to indicate that the current cycle can be
shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An 8-bit
memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no effect
during 16-bit I/O cycles.
If IOCHRDY is negated and ZEROWS# is asserted during the same clock, then
ZEROWS# is ignored and wait states are added as a function of IOCHRDY.
Notes:
1. X-bus signals are 5V tolerant.
2. Since the 440MX does not support the Secondary IDE Channel, IRQ15 is no longer available. However, SERIRQ and PCI
interrupts can be steered to generate Interrupt 15 to the Interrupt controller.
4.1.2
VCC
VSS
POWER AND GROUND PINS
Name
Table 16. Core Power Pins
Description
3.3V for Core. This power is shut off during some low-power states.
VSS Core.
Name
GTLREF
Table 17. Host I/F Power Pins
Description
GTL+ Buffer Voltage Reference input for the mobile Celeron processor or
Pentium II processor I/F.
22