82443MX Datasheet, PDF (148/173 Pages) Intel Corporation – PCIset

82443MX PCIset
The 440MX claims all accesses to these ranges, if enabled. The byte enables do not have to be externally
decoded to assert DEVSEL#. Accesses to byte 3 of the Control Block are forwarded to the X-bus, where the
Floppy controller responds. A 16-bit access to offset 02h of the Control Block (byte enables 2 and 3 asserted)
results in a Target Abort.
Each of the two drives (drive 0 or 1) on a cable implements separate ATA register files. To determine the
targeted drive, the 440MX shadows the value of bit 4 (drive bit) of byte 6 (Drive/Head Register) of the ATA
Command Block (CS1x#) for the IDE connector.
7.12.2 PIO IDE TRANSACTIONS
The 440MX IDE controller includes both compatible and fast timing modes. The fast timing modes can be
enabled only for the IDE data ports. All other transactions to the IDE registers are run in single transaction
mode with compatible timings. The 440MX IDE signals are controlled with the granularity of the PCI clock.
Up to two IDE devices may be attached to the IDE connector (drive 0 and drive 1). The IDETIM and SIDETIM
Registers permit different timing modes to be programmed for drive 0 and drive 1 of the connector.
The Ultra DMA/33 synchronous DMA timing modes can also be applied to each drive by programming the
SDMACTL and SDMATIM Registers. When a drive is enabled for synchronous DMA mode operation, the
DMA transfers are executed with the synchronous DMA timings. The PIO transfers are executed using
compatible timings or fast timings if also enabled.
7.12.3 PIO IDE TIMING MODES
IDE data port transaction latency consists of startup latency, cycle latency and shutdown latency. Startup
latency is incurred when a PCI master cycle targeting the IDE data port is decoded and the PDA[2:0] and
CSxx# lines are not set up. Startup latency provides the setup time for the PDA[2:0] and CSxx# lines prior to
assertion of the read and write strobes (PDIOR# and PDIOW#).
Cycle latency consists of the I/O command strobe assertion length and recovery time. Recovery time is
provided so that transactions may occur back-to-back on the IDE interface (without incurring startup and
shutdown latency) without violating the minimum cycle periods for the IDE interface. The command strobe
assertion width for the enhanced timing mode is selected by the IDETIM Register and may be set to 2, 3, 4, or
5 PCI clocks. The recovery time is selected by the IDETIM Register and may be set to 1, 2, 3, or 4 PCI
clocks. Figure 22 shows how these latencies are related, and how they are summed to produce the overall
transaction latency.
Figure 23 illustrates the case where the PIORDY Sample Point (ISP) is set to two clocks (minimum) and the
Recovery Time (RCT) is set to one clock (minimum).
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