82443MX Datasheet, PDF (74/173 Pages) Intel Corporation – PCIset

82443MX PCIset
series of SMBus I/O cycles. To properly configure the memory interface, the BIOS uses this data to determine
the memory size of each of the four rows.
7.2.2.1.2 SMBUS CONFIGURATION
Before accessing the information from the DIMMs, the SMBus host interface must be initialized. This is done
via two registers mapped to PCI Configuration Space Device #7, function #7. All SMBus accesses are done
through I/O cycles. It is desirable to make the I/O base address programmable to avoid any conflicts with
existing I/O mapped devices in the system. The I/O address is programmed through the 32-bit SMBus Base
Address Register at location 90h, Device #7, function #7. Bits 31:16 of this register are Reserved. Bits 15:4
are used to select the 16-bit base I/O address of the SMBus host controller. Bits 3:1 are Reserved and bit 0 is
hard-wired to 1 indicating that the SMBus host controller is always I/O mapped. The second register to be
configured is the SMBus Host Configuration Register located at D2h, Device #7, function #7. Bits 7:4 of this
register are Reserved. Bits 3:1 are used to assign an interrupt to the SMBus host controller. IRQ9 or SMI#
may be selected. The SMBus host interface is enabled upon setting bit 0 of this register to 1.
7.2.2.1.3 ACCESSING THE SERIAL PRESENCE DETECT PORTS
Each device on the SMBus has a unique seven-bit address. The DRAM DIMMs have the upper four bits of
this address hard-wired as 1010. The remaining three bits are strapped for each DIMM on the SA[2:0] pins.
For example, to support two DIMMs (four rows of memory), the SA[2:0] lines may be strapped to 000 and 001.
Thus, an SMBus cycle with target address 1010000 addresses the lower order DIMM.
Each DIMM contains an EEPROM with up to 256 bytes of accessible data. The BIOS can read this data from
the Serial Presence Detect Ports to determine the type, size and any required attributes of each row of
memory. Once the SMBus host controller is initialized and enabled, accessing the Serial Presence Detect
ports can be done through a sequence of I/O reads and writes to I/O Space Registers defined by the SMBus
base I/O address (see Section 7.2.2.1.2).
7.2.2.1.4 DRAM REGISTER PROGRAMMING
This section provides an overview of how the Serial Presence Detect ports on the DIMMs obtain the required
information to program the DRAM registers. The Serial Presence Detect ports are used to determine Refresh
rate, MA and MD buffer strength, SDRAM timings, row sizes and row page sizes.
Table 41 lists a subset of the data available through the on-board Serial Presence Detect ROM on each
DIMM.
Table 41. Data Bytes on DIMM Used for Programming DRAM Registers
Byte
Function
2
Memory type ( SDRAM)
3
# Row addresses, not counting bank addresses
4
# Column addresses
5
# Banks of DRAM (single- or double-sided DIMM)
11
No ECC
12
Refresh rate
62