82443MX Datasheet, PDF (20/173 Pages) Intel Corporation – PCIset

82443MX PCIset
4.1.1 SIGNAL DESCRIPTION
Signal
A20GATE
A20M#
ADS#
BNR#
BPRI#
BREQ0#
CPURST#
DBSY#
DEFER#
DRDY#
FERR#
HA[31:3]#
HD[63:0]#
Table 2. Host Interface Signal Description
Type
Description
I
Address 20 Gate. This input from the keyboard controller is logically combined
with a bit in Port 92h which is then output via the A20M# signal. A20GATE saves
the external OR gate needed with various other chipsets.
OD Address 20 Mask. A20M# goes active by either setting the appropriate bit in the
Port 92h Register, or by the A20GATE input signal.
I/O
Address Strobe. The processor bus owner asserts ADS# to indicate the first of
two cycles of a request phase.
I/O
Block Next Request. Used to block the current request bus owner from issuing
a new request. This signal is used to dynamically control the processor bus
pipeline depth.
I/O
Priority Agent Bus Request. The 440MX is the only Priority Agent on the
processor bus. The 440MX asserts this signal to obtain the ownership of the
address bus. This signal has priority over symmetric bus requests and will cause
the current symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted.
I/O
Symmetric Agent Bus Request. BREQ0# is asserted during CPURST# to
configure the symmetric bus agents and is negated two host clocks after
CPURST# is negated.
I/O
CPU Reset. The CPURST# pin is an output from the 440MX. The 440MX
generates this signal based on the PCIRST# signal (generated internally from the
South Bridge/Cluster) and the SUS_STAT# pin. CPURST# allows the processor
to begin execution in a known state.
I/O
Data Bus Busy. Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
I/O
Defer. The 440MX generates a deferred response as defined by the 440MX’s
dynamic defer policy. The 440MX also uses the DEFER# signal to indicate a
processor retry response.
I/O
Data Ready. Asserted for each cycle that data is transferred.
I
Numeric Coprocessor Error. This signal is tied to the coprocessor error signal
on the processor. If FERR# is asserted, the 440MX generates an internal IRQ13
to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure
that IGNNE# is not asserted to the processor unless FERR# is active.
I/O
Address Bus. HA[31:3]# connects to the processor address bus. During
processor cycles the HA[31:3]# are inputs. Note that the address bus is inverted
on the processor bus.
I/O
Host Data. These signals are connected to the processor data bus. Note that
the data signals are inverted on the processor bus.
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