82443MX Datasheet, PDF (131/173 Pages) Intel Corporation – PCIset

82443MX PCIset
the Intel Architecture (the 8080 mode of the interrupt controller must never be selected when programming the
440MX).
NOTE:
Externally, the interrupt acknowledge cycle sequence appears to be different than in a traditional
discrete 82C59 implementation. However, the traditional interrupt acknowledge sequence is generated
within the 440MX and is an ISA-compatible implementation.
1. One or more of the Interrupt Request lines (IRQx) are raised high, setting the corresponding IRR bit(s).
2. The Interrupt Controller evaluates these requests, and sends an INTR to the CPU, if appropriate.
3. The CPU acknowledges the INTR and responds with two interrupt acknowledge cycles. The second
cycle is translated into a PCI interrupt acknowledge cycle by the Host Bridge. This command is
broadcast over the PCI as a single cycle as opposed to the two-cycle method typically used.
4. Upon receiving an interrupt acknowledge cycle from PCI, the 440MX South Bridge/Cluster converts the
single cycle into the two cycles that the internal 8259 pair can respond to with the expected interrupt
vector. The cycle conversion is performed by a functional block in the 440MX Interrupt Controller Unit.
The internally generated interrupt acknowledge cycle is completed as soon as possible, as the Host Bus
is held in wait states until the interrupt vector data is returned. Each cycle appears as an interrupt
acknowledge pulse on the INTA# pin of the cascaded interrupt controllers. These two pulses are not
observable at the 440MX periphery.
5. Upon receiving the first internally generated interrupt acknowledge pulse, the highest priority ISR bit is
set and the corresponding IRR bit is reset. The Interrupt Controller does not drive the data bus during
this cycle. On the trailing edge of the first cycle pulse, a slave identification code is broadcast by the
master to the slave on a private, internal three-bit wide bus. The slave controller uses these bits to
determine if it must respond with an interrupt vector during the second INTA# cycle.
6. Upon receiving the second internally-generated interrupt acknowledge, the Interrupt Controller releases
an 8-bit pointer (the interrupt vector) that the 440MX uses to complete the PCI cycle in progress. The
second CPU interrupt acknowledge cycle can now complete on the host bus.
7. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the second
interrupt acknowledge cycle pulse. Otherwise, the ISR bit remains set until an appropriate EOI command
is issued at the end of the interrupt subroutine.
If no interrupt request is present at step four of the sequence (i.e., the request was too short in duration), the
Interrupt Controller issues an interrupt level 7.
7.10.1.2 Interrupt Acknowledge Cycle
The CPU generates an interrupt acknowledge cycle that is translated by the Host Bridge into a single PCI
Interrupt Acknowledge. The interrupt controller translates this command into the two INTA# pulses expected
by the interrupt controller subsystem. The Interrupt Controller uses the first interrupt acknowledge cycle to
internally freeze the state of the interrupts for priority resolution. On the second interrupt acknowledge cycle,
the master (CNTRL-1) or slave (CNTRL-2) sends a byte of data to the processor with the acknowledged
interrupt code composed as shown in Table 71. The byte of data released by the interrupt controller onto the
data bus is referred to as the "interrupt vector”.
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