82443MX Datasheet, PDF (31/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Table 14. GPIO Signal Description
Signal
Default
Type*
Description
GPIO[0,1,2,4,5, Input
6,7,8,9,10,11,
12,13,15,17,18,
20,21,22,23,24,
27,29,30]
General Purpose I/O. Handled by system processor. Some of the 31 GPIO
signals are muxed with other functions. (See Section 4.1.2 for the GPIO
definition.)
3.3V only or 3.3/5V (3.3V drive with 5V tolerant). See Table 24 for details.
GPIO[3,14,16,
19,25,26,28]
Output General Purpose I/O. Handled by system processor. Some of the 31 GPIO
signals are muxed with other functions. (See Section 4.1.2 for the GPIO
definition.)
3.3V only or 3.3/5V (3.3V drive with 5V tolerant). See Table 24 for details.
Note: *This table specifies the default direction of the pins selected as GPIOs (GPIO_DIR Register Dev #7, Function 3, Power
Management I/O Space).
Signal
BIOSCS#
DACK(3)# /
GPIO(28)
DACK(2:0)#
DREQ(3) /
GPIO(27)
DREQ(2:0)
IOCHRDY
Table 15. X-bus Signal Description
Type
Description
O
ROM BIOS Chip Select. This chip select is driven active during read or write
accesses to enabled BIOS memory ranges.
I/O
DMA Acknowledge. The DACK output lines indicate that a request for DMA
service has been granted by the 440MX. These lines should be used to decode
the DMA slave device with the IOR# or IOW# line to indicate selection. Upon
PCIRST#, these lines are set inactive (high). DACK3# is muxed with GPIO(28).
O
DMA Acknowledge. The DACK output lines indicate that a request for DMA
service has been granted by the 440MX. These lines should be used to decode
the DMA slave device with the IOR# or IOW# line to indicate selection. Upon
PCIRST#, these lines are set inactive (high).
I/O
DMA Request. The DREQ lines are used to request DMA service from the
440MX's DMA controller. All inactive to active edges of DREQ are assumed to
be asynchronous. The request must remain active until the appropriate DACKx#
signal is asserted.
DREQ3 is muxed with GPIO(27).
I
DMA Request. The DREQ lines are used to request DMA service from the
440MX's DMA controller. All inactive to active edges of DREQ are assumed to
be asynchronous. The request must remain active until the appropriate DACKx#
signal is asserted.
I/O
I/O Channel Ready. Resources on the X-bus de-assert IOCHRDY to indicate
that additional time (wait states) is required to complete the cycle. This signal is
normally high on the X-bus.
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