82443MX Datasheet, PDF (57/173 Pages) Intel Corporation – PCIset

82443MX PCIset

Above 1-MB option that allows new SMI handlers to execute with write-back cacheable SMRAM.

Optional larger write-back cacheable T_SEG area, from 128 KB to 1 MB in size, above 1 Mbyte. This
area is located just below the top of main memory.
Both of the above 1-Mbyte solutions require changes to compatible SMRAM handler code to properly execute
above 1 Mbyte.
6.4 Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be “shadowed” into main
memory. Typically this is done to allow ROM code to execute more rapidly out of main DRAM. To achieve
this, ROM is designated read-only during the copy process while at the same time DRAM is designated write-
only. After copying, the DRAM is designated read-only so that ROM is shadowed. Processor bus transactions
are routed accordingly.
6.5 Decode Rules and Cross-Bridge Address Mapping
The address map described above, with the exception of SMRAM, applies globally to accesses arriving on
either the host bus or the external PCI bus. Accesses initiated from any of the other peripheral buses, other
than the host bus and the external PCI bus (e.g., USB, IDE), are only allowed to access main memory, and
must not attempt to access any other memory space on or behind the 440MX.
6.5.1 PCI INTERFACE MEMORY DECODE RULES
All memory read and write accesses are accepted from the external PCI bus that are targeted to main DRAM.
PCI accesses that fall elsewhere within the PCI memory range will not be claimed. This implies that external
PCI devices cannot access BIOS memory on the X-bus.
6.5.2 LEGACY VGA RANGE
The legacy VGA memory range A0000h-BFFFFh is always mapped to the external PCI bus in Normal mode.
(In SMM, it is mapped to main memory.)
6.6 I/O Address Space
For all processor-initiated I/O accesses, cycles are internally terminated, or bus cycles are generated on the
internal PCI bus. The cycles generated on the internal PCI bus can be one of two types:

PCI configuration cycles

PCI I/O cycles
For the purpose of converting I/O cycles to PCI configuration cycles, two internal registers are used. These
registers are located in the processor I/O space, the Configuration Address Register (CONFIG_ADDRESS)
and the Configuration Data Register (CONFIG_DATA). These registers are used to implement the PCI
configuration space access mechanism as described in the PCI configuration section. If the PCI
Configuration Register accessed via the I/O space is internal to the 440MX North Bridge/Cluster, the cycle will
not be generated on the internal PCI bus.) If the PCI Configuration Register accessed is not internal to the
440MX North Bridge/Cluster, the cycle will be generated on the internal PCI bus and also broadcast to the
external PCI bus.
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