82443MX Datasheet, PDF (73/173 Pages) Intel Corporation – PCIset

Figure 6 depicts the 440MX connections for a two-DIMM SDRAM memory array.
CS[3:2]#
CS[1:0]#
SRAS#
SCAS#
WE#
MA[13,12#,
11#,10,(9:0)#]
MD[63:0]
DQM[7:0]
CKE[3:2]#
CKE[1:0]#
CLK[7:4]
CLK[3:0]
SMB_CLK
SMB_DATA
DIMM0
DIMM1
82443MX PCIset
Figure 6. DIMM Configuration with FET Switches
7.2.2.1 Configuration Mechanism for DIMMs
Detection of the DRAM type installed on the DIMM is supported via the Serial Presence Detect mechanism as
defined in the JEDEC 168-pin DIMM standard. This standard uses the SCL (SMB_CLK), SDA (SMB_DATA)
and SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special programmable
modes are provided for detecting the size and type of memory installed. Type and size detection must be
done via the serial presence detection pins.
7.2.2.1.1 MEMORY DETECTION AND INITIALIZATION
The DRAM registers must be initialized before any cycles to the memory interface can be supported.
Detection of memory size is done via the System Management Bus (SMBus). This two-wire bus is used to
extract the DRAM type and size information from the serial presence detect port on the DRAM DIMMs.
DRAM DIMMs contain a five-pin serial presence detect interface, including SCL (serial clock), SDA (serial
data) and SA[2:0]. Each device on the SMBus bus has a seven-bit address. For the DRAM DIMMs, the
upper four bits are fixed at 1010. The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are
connected directly to the SMBus. Thus, data is read from the Serial Presence Detect port on the DIMMs via a
61