82443MX Datasheet, PDF (102/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Channel 0
Channel 1
Channel 2
Channel 3
DMA-1
Channel 4
Channel 5
Channel 6
Channel 7
DMA-2
SIO-45.DRW
Figure 12. Internal DMA Controller
Note that any DMA device (I/O device) always resides on the X-bus, and that the referenced memory is
located in system memory. When the 440MX is running a compatible DMA cycle, it drives the MEMR# and
MEMW# strobes if the address is less than 16 Mbytes (000000h - FFFFFFh). If the address is greater than
16 Mbytes (1000000h - 7FFFFFFh), the MEMR# or MEMW# strobe are not generated in order to avoid
aliasing problems.
Also, during DMA memory read cycles to the PCI bus, the 440MX returns all 1's to the X-bus if the PCI cycle
is either target aborted or master aborted.
7.6.2.1 DMA Transfer Modes
DMA channels can be programmed for any of three transfer modes: single, block and demand. Each of the
active transfer modes can perform three different types of transfers (read, write, or verify). Note that memory-
to-memory transfers are not supported.
7.6.2.1.1 SINGLE TRANSFER MODE
In single transfer mode, the DMA is programmed to make one transfer only. The byte/word count is
decremented and the address decremented or incremented following each transfer. When the byte/word
count "rolls over" from zero to FFFFh, a Terminal Count (TC) causes an auto-initialize if the channel has been
programmed to do so.
To be recognized, DREQ must be held active until DACK# becomes active. If DREQ is held active throughout
a single transfer, the bus is released after the single transfer. With DREQ asserted high, the DMA I/O device
re-arbitrates for the bus. Upon winning the bus, another single transfer is performed.
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