82443MX Datasheet, PDF (156/173 Pages) Intel Corporation – PCIset

82443MX PCIset
0ns
250ns
500ns
750ns
SYSCLK
ZEROWS#
IOCHRDY
IOR#/IOW#
d
d
d
a
b
c
a
b
c
d
e
e
a
b
c
d
e
Notes:
a. 8-bit compressed I/O (@ 3 SYSCLKs)
b. 8-bit compressed I/O (@ 4 SYSCLKs)
c. 8-bit compressed I/O (@ 5 SYSCLKs)
d. 8-bit standard I/O (@ 6 SYSCLKs)
e. 8-bit extended I/O (@ 7 SYSCLKs)
Figure 25. ISA 8-bit I/O Cycles
7.13.2 X-BUS CLOCK (SYSCLK) GENERATION
The 440MX generates the X-bus system clock, SYSCLK. SYSCLK is based on a divide-by-4 of PCICLK and
has a frequency of 8.25 MHz, based on a PCICLK frequency of 33 MHz. SYSCLK may be stretched to speed
up accesses to the X-bus. When the 440MX stops PCICLK, it also stops SYSCLK.
7.13.3 WAIT STATE AND SHORTENED CYCLE GENERATION
The 440MX adds wait states during I/O target cycles to the X-bus if IOCHRDY is sampled de-asserted. Wait
states are added as long as IOCHRDY is low.
The 440MX shortens the I/O target cycles (not including DMA) if ZEROWS# is sampled active.
NOTE:
If IOCHRDY is sampled de-asserted and ZEROWS# is sampled asserted simultaneously, the
IOCHRDY level takes precedence and wait states will be added.
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