82443MX Datasheet, PDF (108/173 Pages) Intel Corporation – PCIset

82443MX PCIset
with the Current Registers by the microprocessor when the DMA channel is programmed and remain
unchanged throughout the DMA service. The mask bit is not set when the channel is in Autoinitialize.
Following Autoinitialize, the channel is ready to perform another DMA service, without CPU intervention, as
soon as a valid DREQ is detected.
7.6.2.6 Software Commands
The three additional special software commands that can be executed by the DMA controller are:

Clear Byte Pointer Flip- Flop

Master Clear

Clear Mask Register
These software commands do not depend on any specific bit pattern on the data bus.
7.6.2.6.1 CLEAR BYTE POINTER FLIP-FLOP
This command is executed prior to writing or reading new address or word count information to/from the DMA
controller. This initializes the flip-flop to a known state so that subsequent accesses to register contents by the
microprocessor will address upper and lower bytes in the correct sequence.
When the host CPU is reading or writing DMA registers, two byte-pointer flip-flops are used; one for channels
0-3 and one for channels 4-7. Both of these act independently and each is cleared by separate software
commands (0Ch for channels 0-3, 0D8h for channels 4-7).
7.6.2.6.2 DMA MASTER CLEAR
This software instruction has the same effect as a hardware reset. The Command, Status, Request, and
Internal First/Last Flip-Flop Registers are cleared and the Mask Register is set. The DMA controller enters the
idle cycle.
The two independent master clear commands are:

0Dh acts on Channels 0-3

0DAh acts on Channels 4-7
7.6.2.6.3 CLEAR MASK REGISTER
This command clears the mask bits of all four channels, enabling them to accept DMA requests. I/O port
00Eh is used for channels 0-3 and I/O port 0DCh is used for channels 4-7.
7.6.2.7 Terminal Count Summary
Table 60 summarizes the events that occur as a result of a terminal count when running DMA in various
modes.
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