82443MX Datasheet, PDF (125/173 Pages) Intel Corporation – PCIset

82443MX PCIset
1. Read least significant byte.
2. Write new least significant byte.
3. Read most significant byte.
4. Write new most significant byte.
If a counter is programmed to read/write two-byte counts, a program must not transfer control between
reading the first and second byte to another routine that also reads from that same counter. Otherwise, an
incorrect count is read.
7.8.3.3.1 READ BACK COMMAND
The Read Back command determines the count value, programmed mode, and current states of the OUT pin
and Null Count flag of the selected counter or counters. The Read Back command is written to the Control
Word Register, which causes the current states of the above mentioned variables to be latched. The value of
the counter and its status may then be read by I/O access to the counter address.
The Read Back command may be used to latch multiple counter output latches (OL) by setting the COUNT#
bit D5=0 and selecting the desired counter(s). This single command is functionally equivalent to several
counter latch commands, one for each counter latched. Each counter's latched count is held until it is read (or
the counter is reprogrammed). Once read, a counter is automatically unlatched. The other counters remain
latched until they are read. If multiple count Read Back commands are issued to the same counter without
reading the count, all but the first are ignored (i.e., the count that is read is the count at the time the first Read
Back command was issued).
The Read Back command may also be used to latch status information of selected counter(s) by setting
STATUS# bit D4=0. The status must be latched to be read. The status of a counter is accessed by a read
from that counter's I/O port address.
If multiple counter status latch operations are performed without reading the status, all but the first are
ignored. The status returned from the read is the counter status at the time the first status Read Back
command was issued.
Both count and status of the selected counter(s) may be latched simultaneously by setting both the COUNT#
and STATUS# bits [5:4]=00. This is functionally the same as issuing two consecutive, separate Read Back
commands. The above discussions apply here also. Specifically, if multiple count and/or status Read Back
commands are issued to the same counter(s) without any intervening reads, all but the first are ignored.
If both the count and status of a counter are latched, the first read operation from that counter returns the
latched status, regardless of which was latched first. The next one or two reads (depending on whether the
counter is programmed for one- or two-type counts) return the latched count. Subsequent reads return an
unlatched count.
7.9 RTC
7.9.1 RTC OVERVIEW
The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two
banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose usage.
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