82443MX Datasheet, PDF (159/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.14.2 SMBUS SLAVE INTERFACE
The 440MX supports three separate mechanisms for SMBus peripherals to communicate to the 440MX. In
addition to transferring data, these mechanisms can generate an interrupt or resume the system from a
Suspend state.
The first mechanism consists of accesses to the SMBus controller host slave port at address 10h. (Note that
this address is actually 0001 000x as this is a 7-bit address (bits[7:1]) with bit 0 being an R/W bit.) The host
slave port responds to Word Write transactions only with the incoming data being stored in the SMBSLVDAT
Register and incoming command in the SMBSHDWCMD Register. An interrupt or Resume event is generated
(if enabled) if the incoming command matches the command stored in the SMBSLVC Register and at least
one bit read into the SMBSLVDAT Register matches with the corresponding bit in the SMBSLVEVT Register.
The second mechanism monitors accesses to the SMBus controller slave shadow ports at addresses stored
in the SMBSHDW1 and SMBSHDW2 Registers. The shadow slave ports responds to Word Write transactions
only with the incoming data being stored in the SMBSLVDAT Register and incoming command being stored in
the SMBSHDWCMD Register. An interrupt or Resume event is generated (if enabled) when the slave shadow
ports are accessed.
The SLV_BSY bit indicates that the 440MX slave interface is receiving an incoming message. The
SMBSLVCNT, SMBSHDWCMD, SMBSLVEVT, SMBSLVDAT, and SMBSLVC Registers should not be
accessed while the SLV_BSY bit is active (until completion of transaction).
The third method for SMBus devices to communicate with the 440MX is with the SMBALERT# signal. When
enabled and the SMBALERT# signal is asserted, the 440MX generates an interrupt or resumes the system
from a Suspend state. This simple mechanism allows a device without SMBus master capabilities to request
service from the SMBus host (440MX). To determine which device asserted the SMBALERT# signal, the
440MX host controller should be programmed to execute a read command using the Alert Response Address.
Once the slave interface has received a transaction and generated an interrupt, it stops responding to new
requests until all interrupt status bits in the SMBSLVSTS Register are cleared.
7.15 GPIO
The 440MX contains 31 general-purpose input and output signals that can be used for system customization.
The signals are grouped into the following two categories:

General Purpose Outputs (GPO) Standard non three-stateable outputs

General Purpose Inputs (GPI) Standard input
Depending on the general configuration, not all of the GPIO signals will be available because they may be
used for some other dedicated function.
7.15.1 CONFIGURATION
The 440MX signals are configured through the PCI Configuration Function 0, Registers B0-B3, D4-DB, E0-E3.
The BIOS must set the configuration of the signals before attempting to use them.
The General Signal and Configuration Register (Device #7, Function 0 PCI Config Space) bits that affect the
following GPIOs: REQA#, GNTA#, SERIRQ and IRQ8# remain in the same power plane (i.e., the core power
plane). GPI_REG:32 (Dev #7, Function 3, Power Management I/O Space) is in the core well and is reset by
PCIRST# (not RSMRST#).
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