82443MX Datasheet, PDF (52/173 Pages) Intel Corporation – PCIset

82443MX PCIset
6.
SYSTEM ADDRESS MAP
6.1 Addressable Memory Support
A mobile Celeron processor system based on the 440MX supports 4 GB of addressable memory space and
64K+3 bytes of addressable I/O space. (The mobile Celeron processor bus I/O addressability is 64K+3 bytes.)
The programmable memory address space under the 1 MB region which is divided into regions can be
individually controlled with programmable attributes such as Disable, Read/Write, Write Only, or Read Only.
Attribute programming is described in the Programmable Attribute Map Registers in PCI configuration space.
This section focuses on how the memory space is partitioned and how these separate memory regions are
used. The I/O address space is explained at the end of this section.
Although the Pentium II processor family supports addressing of memory ranges larger than 4 GB, it is
assumed that software running on a the 440MX system will never address physical memory above 4 GB (see
Figure 3).
6.2 Memory Map
NOTE:
The internal PCI bus between the North Bridge/Cluster and the South Bridge/Cluster is PCI bus
number 0. All cycles from the North Bridge/Cluster or external PCI bus that appear on the internal PCI
bus are either positively or subtractively decoded by the South Bridge/Cluster, depending on the mode
selected. All cycles from the South Bridge/Cluster or external PCI bus that appear on the internal PCI
bus are positively decoded by the North Bridge/Cluster and claimed only if there is an address match.
Cycles between the North and South Bridge/Cluster are also broadcast to the external PCI bus. Thus
the external PCI bus which interfaces to other PCI devices is logically the same bus as the internal PCI
bus, i.e., PCI bus #0.
Table 32 summarizes the memory address space supported. The WE and RE attributes refer to Write Enable
and Read Enable.
40