82443MX Datasheet, PDF (95/173 Pages) Intel Corporation – PCIset

82443MX PCIset
440MX
North Bridge / Cluster
PCI Bus
South Bridge / Cluster
Figure 11. 440MX PCI Bus Topology
7.5.2 NORTH BRIDGE/CLUSTER FUNCTIONALITY
7.5.2.1 North Bridge/Cluster as a PCI Target
Table 53 summarizes the PCI transactions supported by the North Bridge/Cluster when acting as a target.
Table 53. PCI Commands Supported by the North Bridge/Cluster when Acting as a PCI Target
PCI Command
C/BE[3:0]#
440MX North Bridge/Cluster
Encoding
Cycle Destination
Response as PCI Target
Interrupt Acknowledge
0000
N/A
No Response
Special Cycle
0001
N/A
No Response
I/O Read
0010
N/A
No Response
I/O Write
0011
N/A
No Response
Reserved
0100
N/A
No Response
Reserved
0101
N/A
No Response
Memory Read
0110
Main Memory
Short Read
Memory Write
0111
Main Memory
Posts Data
Reserved
1000
N/A
No Response
Reserved
1001
N/A
No Response
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