82443MX Datasheet, PDF (5/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.2.6.3
Selective Auto Precharge Policy ............................................................... 70
7.2.7 DRAM Power Throttling .................................................................................................. 71
7.2.7.1
Overview................................................................................................... 71
7.2.7.2
Conceptual Description of Power Throttling............................................... 71
7.2.7.3
SDRAM Power Throttling Setting Sequence ............................................. 72
7.2.8 SDRAM Performance Description................................................................................... 73
7.2.9 SDRAM Optimizations .................................................................................................... 73
7.2.9.1
Dual and Quad Bank Support.................................................................... 73
7.3 System Memory Management ...................................................................................................... 73
7.3.1 SMRAM range overview ................................................................................................. 73
7.3.2 Compatible SMRAM (C_SMRAM) .................................................................................. 74
7.3.3 Extended SMRAM (E_SMRAM) ..................................................................................... 74
7.4 AC’97 Audio and Modem Controller.............................................................................................. 77
7.4.1 AC’97 Audio Controller....................................................................................................77
7.4.2 AC’97 Modem Controller................................................................................................ 78
7.4.3 AC’97 Overview .............................................................................................................. 78
7.4.4 System Initialization ........................................................................................................ 80
7.4.5 Clocking.......................................................................................................................... 80
7.4.6 Digital Interface............................................................................................................... 80
7.4.6.1
Multi-Point ACLink..................................................................................... 80
7.4.6.2
AC-link Digital Serial Interface Protocol..................................................... 81
7.5 PCI Interface ................................................................................................................................ 82
7.5.1 PCI Interface Overview ................................................................................................... 82
7.5.2 North Bridge/Cluster Functionality................................................................................... 83
7.5.2.1
North Bridge/Cluster as a PCI Target ........................................................ 83
7.5.2.2
North Bridge/Cluster as a PCI Initiator....................................................... 84
7.5.2.3
Delayed Transactions ............................................................................... 86
7.5.3 South Bridge/Cluster Functionality .................................................................................. 87
7.5.3.1
South Bridge/Cluster as a PCI Target ....................................................... 87
7.5.3.2
South Bridge/Cluster as a PCI Initiator...................................................... 88
7.6 DMA Controller ............................................................................................................................. 89
7.6.1 Register Description........................................................................................................ 89
7.6.2 Functional Description ....................................................................................................89
7.6.2.1
DMA Transfer Modes ................................................................................ 90
7.6.2.2
DMA Transfer Types ................................................................................. 91
7.6.2.3
DMA Timings ............................................................................................ 92
7.6.2.4
X-bus / DMA Arbitration ............................................................................ 92
7.6.2.5
Register Functionality................................................................................ 94
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