82443MX Datasheet, PDF (67/173 Pages) Intel Corporation – PCIset

82443MX PCIset
RS2# RS1# RS0#
Description
440MX Support
transferred. Writes and zero length reads receive this
response.
1
1
0
Implicit Writeback
This response is generated for transactions that hit a
modified cache line.
1
1
1
Normal Data Response This response is for transactions where data
accompanies the response phase. Reads receive this
response.
7.1.3 SPECIAL CYCLES
A special cycle is defined when REQa[4:0]=01000 and REQb[4:0]=xx001. The first address phase, Aa[35:3]#
is undefined and can be driven to any value. The second address phase, Ab[15:8]# defines the type of special
cycle issued by the processor.
Table 38 specifies the cycle type and definition, as well as the action by the 440MX when the corresponding
cycles are identified.
Table 38. Special Cycle Transactions
BE[7:0}# Special Cycle
Type
Action Taken
0000 0000 NOP
This transaction has no effect.
0000 0001 Shutdown
This transaction is issued when an agent detects a severe software error that
prevents further processing. This cycle is claimed by the 440MX, which issues
a shutdown special cycle on the PCI bus. This cycle is retired on the CPU bus
after it is terminated on the PCI via a master abort mechanism.
0000 0010 Flush
This transaction is issued when an agent has invalidated its internal caches
without writing back any modified lines. The 440MX claims this cycle and retires
it.
0000 0011 Halt
This transaction is issued when an agent executes an HLT instruction and stops
program execution. This cycle is claimed by the 440MX and propagated to PCI
as a Special Halt Cycle. This cycle is retired on the CPU bus after it is
terminated on the PCI via a master abort mechanism.
0000 0100 Sync
This transaction is issued when an agent has written back all modified lines and
has invalidated its internal caches. The 440MX claims this cycle and retires it.
0000 0101 Flush
This transaction is issued when an agent has completed a cache sync and flush
Acknowledg operation in response to an earlier FLUSH# signal assertion. The 440MX claims
e
this cycle and retires it.
0000 0110 Stop Clock
Acknowledg
e
This transaction is issued when an agent enters Stop Clock mode. This cycle is
claimed by the 440MX and propagated to the PCI as a Special Stop Grant
cycle. This cycle is completed on the CPU bus after it is terminated on the PCI
via a master abort mechanism.
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