82443MX Datasheet, PDF (100/173 Pages) Intel Corporation – PCIset

82443MX PCIset
PCI Command
C/BE[3:0]#
Encoding
Memory Write and
Invalidate
1111
Note:
N/A refers to a function that is not applicable.
Notes
Aliased to Memory Write
7.5.3.2 South Bridge/Cluster as a PCI Initiator
The South Bridge/Cluster initiates cycles on the PCI bus on behalf of IDE, DMA, USB, and X-bus when
granted by the arbiter.
Table 56 shows that, as an initiator on the PCI bus, the South Bridge/Cluster can only generate memory and
I/O read/write cycles.
Table 56. PCI Commands Supported by the South Bridge/Cluster when Acting as a PCI Initiator
PCI Command
C/BE[3:0]#
Encoding
Notes
Interrupt
0000
N/A
Acknowledge
Special Cycle
0001
N/A
I/O Read/
I/O Write
0010/
0011
Supported
Reserved
0100
N/A
Reserved
0101
N/A
Memory Read/
Memory Write
0110/
0111
Supported
Reserved
1000
N/A
Reserved
1001
N/A
Configuration Read 1010
N/A
Configuration Write 1011
N/A
Memory Read
1100
N/A
Multiple
Dual Address Cycle 1101
N/A
Memory Read Line 1110
N/A
Memory Write and 1111
N/A
Invalidate
Note:
N/A refers to a function that is not applicable.
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