82443MX Datasheet, PDF (106/173 Pages) Intel Corporation – PCIset

82443MX PCIset
(4-Way Rotation)
DMAx
CH5
Ch6
CH7
(4-Way Rotation)
CH0
CH1
Ch2
CH3
IBISAARB.drw
Figure 14. X-Bus Arbiter with DMA in Rotating Priority
Table 57. Rotating Priority Example
Programmed Mode
Action
Priority
High...............Low
Group (0-3) is in rotation mode
1) Initial Setting
(0, 1, 2, 3), 5, 6, 7
Group (4-7) is in fixed mode.
2) After servicing channel 2
(3, 0, 1, 2), 5, 6, 7
3) After servicing channel 3
(0, 1, 2, 3), 5, 6, 7
Group (0-3) is in rotation mode
1) Initial Setting
(0, 1, 2, 3), 5, 6, 7
Group (4-7) is in rotation mode
2) After servicing channel 0*
5, 6, 7, (1, 2, 3, 0)
3) After servicing channel 5
6, 7, (1, 2, 3, 0), 5
4) After servicing channel 6
7, (1, 2, 3, 0), 5, 6
5) After servicing channel 7
Note:
*The first servicing of Channel 0 caused double rotation.
(1, 2, 3, 0), 5, 6, 7
7.6.2.4.2 ARBITRATION DURING NON-MASKABLE INTERRUPTS
If a non-maskable interrupt (NMI) is pending, then the DMA controller is bypassed each time it comes up for
rotation. This gives the CPU the bus bandwidth it requires to process the interrupt as fast as possible.
7.6.2.5 Register Functionality
DMA Channel 4 is used to cascade the two DMA controllers together and should not be programmed for any
mode other than cascade. The DMA Channel Mode Register for channel 4 defaults to cascade mode. Special
attention should also be taken when programming the Command and Mask Registers as related to Channel 4.
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