82443MX Datasheet, PDF (17/173 Pages) Intel Corporation – PCIset

82443MX PCIset
2.
ARCHITECTURE OVERVIEW
The 440MX is a single-component chipset that integrates the North Bridge and the South Bridge, and an
additional AC’97 digital link (2 channels) into one chip. It replaces the ISA interface with an 8-bit X-bus that
supports KBC, SIO and Flash memory. Figure 1 illustrates a block diagram of the 440MX platform.
AC'97 Codec
3.3V, 2
chn.
Clock Gen.
GPIO
SIO
Flash
Keyboard
& PS/2
Intel
Mobile Celeron^TM Processor /
Pentium^TM II Processor
66 MHz, GTL Processor i/f
AC'97
Link (2
chn.)
Central
Unit
&
Memory
Controller
66 MHz
3.3V
Bus Controller
PCI 2.2
(3.3V, 32 bit,
33 MHz)
GPIO
North Bridge/
Cluster
8-bit
X- bus
IDE Controller
(1 chn.)
USB
(1 HCI)
Power
Management
Control
SM Controller
(1 chn.)
South Bridge/
Cluster
System Memory
(SDRAM)
System MDeIMmMor#y0
(SDRAM)
DIMM#1
Graphic
Controller
LCD Panel
CRT
CardBus
Controller
IDE Drive
(2)
USB
(2 ports)
Power Management
SMBus
Figure 1. 440MX Platform Block Diagram
5