82443MX Datasheet, PDF (104/173 Pages) Intel Corporation – PCIset

82443MX PCIset
7.6.2.3 DMA Timings
ISA-compatible timing is provided for DMA slave devices that reside on the X-bus.
7.6.2.3.1 DMA BUFFER FOR COMPATIBLE TRANSFERS
The DMA buffer is a 4-byte buffer that is used to reduce the PCI utilization resulting from DMA transfers by X-
bus devices.
When the DMA buffer contains data read from a PCI slave that is destined to be transferred to a DMA slave, it
is in the "read state." Data is discarded when there is a change in X-bus ownership as indicated by any
DACK# signal going inactive.
When the DMA buffer contains data from an X-bus DMA slave that is to be written to a PCI slave, it is in the
"write state". The 4-byte buffer is flushed when it becomes full. The buffer is also flushed whenever there is a
change in X-bus ownership as indicated by any DACK# signal going inactive. A subsequent DMA cycle will be
delayed until the flush is complete.
Once the buffer is scheduled to be flushed to PCI, any PCI master read cycle to the South Bridge/Cluster, X-
bus or IDE is retried by the South Bridge/Cluster (writes must not be retried or a "livelock" condition occurs).
Reads are retried because PCI masters cannot be allowed to observe the state changes in devices connected
to the X-bus or in the DMA controller itself resulting from the DMA transfer until the data from that DMA
transfer is visible in system memory.
7.6.2.3.2 DREQ AND DACK# LATENCY CONTROL
The 440MX DMA arbiter maintains a minimum DREQ-to-DACK# latency on all DMA channels when
programmed in compatible mode. This is to support older devices such as the 8272A. The DREQs are
delayed by eight SYSCLKs prior to being seen by the arbiter logic. This delay guarantees a minimum 1 s
DREQ-to-DACK# latency. Software requests do not have this minimum request to DACK# latency.
7.6.2.4 X-bus / DMA Arbitration
The X-bus arbiter evaluates requests for the X-bus coming from three different sources. PCI masters have
default ownership of the X-bus, while the DMA unit may request access to the X-bus through the 440MX
arbiter. The DMA unit provides a preliminary layer of arbitration for requests from DMA channels.
PCI master cycles have default priority over the 440MX arbiter. The 440MX’s X-bus arbiter uses a simple two-
way rotating priority arbitration method. The 440MX arbitrates for X-bus control through the internal PCI
PHOLD# / PHLDA# protocol when a DMA request is pending.
If the 440MX performs a PCI transaction as a master on behalf of the DMA controller and that transaction is
terminated with a retry, the 440MX reissues the transaction without de-asserting the internal PHOLD#.
(PHOLD# cannot be de-asserted without creating a deadlock situation.)
Devices are serviced according to their rotation position, independent of the order in which they assert a bus
request. This arbitration normally rotates priority after either agent is granted the bus.
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