82443MX Datasheet, PDF (124/173 Pages) Intel Corporation – PCIset

82443MX PCIset
If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must
not transfer control between writing the first and second byte to another routine that also writes into that same
counter. Otherwise, the counter is loaded with an incorrect count. The count must always be completely
loaded with both bytes.
7.8.3.2.1 READ OPERATIONS
The 440MX timer unit allows the value of a counter to be read without disturbing the count in progress.
The following sections describe the three possible methods for reading the counters: a simple read operation,
the Counter Latch Command, and the Read-Back Command.
7.8.3.2.2 COUNTER I/O PORT READ
This method performs a simple read operation. To read the counter, which is selected with the A1, A0 inputs
(port 040h, 041h, or 042h), the CLK input of the selected counter must be inhibited by using either the GATE
input or external logic. Otherwise, the count may be in the process of changing when it is read, giving an
undefined result. When reading the count value directly, follow the format programmed in the Control
Register: read LSB, read MSB, or read LSB then MSB. Within the 440MX timer unit, the GATE input on
Counter 0 and Counter 1 is tied high. Therefore, the direct register read should not be used on these two
counters. The GATE input of Counter 2 is controlled through I/O port 061h. If the GATE is disabled through
this register, direct I/O reads of port 042h return the current count value.
7.8.3.3 Counter Latch Command
The Counter Latch Command latches the count when the command is received. This command is used to
ensure that the count read from the counter is accurate (particularly when reading a two-byte count). The
count value is then read from each counter's Count Register as was programmed by the Control Register.
The selected counter's output latch (OL) latches the count at the time the Counter Latch command is
received. This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed). The
count is then unlatched automatically and the OL returns to "following" the counting element (CE). This allows
the counters’ contents to be read "on the fly" without affecting the count in progress. Multiple Counter Latch
commands may be used to latch more than one counter. Each latched counter's OL holds its count until it is
read. Counter Latch commands do not affect the programmed mode of the counter in any way. The Counter
Latch command can be used for each counter in the 440MX timer unit.
If a Counter is latched and then, some time later, latched again before the count is read, the second Counter
Latch command is ignored. The count read is the count at the time the first Counter Latch command was
issued.
With either method, the count must be read according to the programmed format; specifically, if the counter is
programmed for two-byte counts, two bytes must be read. The two bytes do not have to be read one right
after the other. Read, write, or programming operations for other counters may be inserted between them.
Another feature of the 440MX timer is that reads and writes of the same counter may be interleaved. For
example, if the Counter is programmed for two-byte counts, the following sequence is valid:
112