82443MX Datasheet, PDF (30/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Signal
Type
Description
PWRBTN#
I
Power Button. This signal causes the SMI# or SCI to request that the system
enter a Sleep state. If already in a Sleep state, it causes a wake event. If
PWRBTN# is pressed for four seconds, it causes an unconditional transition
(power button override) to the S5 state with only the PWRBTN# available as a
wake event. An override occurs even if the system is in the S1-S4 states.
PWROK
I
Power OK. When asserted, PWROK is an indication to the 440MX that STR
(Suspend-to-RAM) power plane and PCICLK has been stable for at least 1 ms.
PWROK can be driven asynchronously. When PWROK is negated, the 440MX
asserts PCIRST# and RSTDRV. It also resets the processor.
RI# / GPIO(12) I / I/O
Ring Indicate. When asserted, this signal indicates that a telephone ringing
signal has been received by the modem and that the 440MX should wake up the
system to accept data from the call. This signal is muxed with GPIO(12).
RSMRST#
I
Resume Well Reset. Used for resetting the Resume well. If using a PS’98
power supply, then no external RC circuit is required. Otherwise, a 1 ms delay is
needed.
SUS_STAT# O
Suspend Status. This signal is asserted by the 440MX to indicate that the
system will be entering a low-power state soon. It can be used by peripherals as
an indication that they should isolate their outputs that may be going to powered-
off planes.
SUSA#
O
Power plane control. Shuts off power to all non-critical systems when in the S1
(Power-On Suspend) or S2 (Power-On Suspend w/ full Reset) state. This signal
goes low to turn off the power.
SUSB#
O
Power plane control. Shuts off power to all non-critical systems when in the S3
(Suspend-to-RAM) state. This signal goes low to turn off the power.
SUSC#
O
Power plane control. Shuts power to all non-critical systems when in the S4
(Suspend-to-Disk) or S5 (Soft Off) states. This signal goes low to turn off the
power.
SUSCLK
O
Suspend Clock. 32.768 KHz. This output signal from the Real Time Clock
generator circuit is used as the Refresh clock for the 440MX. This signal is
always running, except in the Suspend-to-Disk or Soft-Off states.
During Reset: Running
After Reset:
Running
During POS, STR: Running
THRM# /
GPIO(8)
I / I/O
Thermal Alarm. Active low signal generated by external hardware to start the
Hardware clock throttling mode. This signal can also generate an SMI# or an
SCI. This signal is muxed with GPIO(8).
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