82443MX Datasheet, PDF (87/173 Pages) Intel Corporation – PCIset

82443MX PCIset
DRAM Area
A, B Segments
TSEG
Table 48. Extended SMRAM DRAM Memory Regions
Size/Availability
64 Kbytes always available if enabled (i.e., G_SMRAME = 1 and H_SMRAME=’1’)
128K, 256K, 512K or 1 MB available if enabled (i.e., TSEG_EN=1 and G_SMRAME = 1)
As with the Compatible SMRAM solution, the 440MX does not claim any bus master access to the Extended
SMRAM memory ranges defined earlier. The D-OPN, DLCK and D_CLS bits provide the same functions as
in compatible SMRAM. The CPU can access these memory ranges by one of the following mechanisms:

The processor can access SMRAM while in the SMM mode. A processor access to SMRAM while not in
SMM and while the D_OPN bit is reset, is forwarded to the PCI bus and a status bit is set in the
SMRAMC Register.

The processor can access SMRAM while the D_OPN bit is set.
Figure 7 illustrates how SMRAM is mapped for various SMRAM ranges.
Table 49 summarizes the operation of SMRAM space cycles targeting the SMI space addresses. The
compatible SMRAM region at “A” is always available. The H_SRMAME bit controls accesses to the High
SMRAM range “H”. The TSEG_EN bit independently controls the extended SMRAM range “T”.
SMRAM regions are decoded as follows:
A = 0A0000 to 0BFFFFh
H = 100A0000h to 100FFFFFh
T = (256M + TOM-Segment) to (256M + TOM)
Table 50 defines the decode control for all code fetches and data fetches to SMRAM ranges (as defined by
Table 49). The G_SMRAM bit provides a global disable for all SMRAM memory. The D_OPEN bit allows
software to write to the SMRAM ranges without being in SMM. BIOS software can use this bit to initialize
SMM code at powerup. The D_LCK bit limits the SMRAM range access to only SMM mode accesses. The
D_CLS bit causes SMM data accesses to be forwarded to PCI. The SMM software can use this bit to write to
video memory while running code out of DRAM.
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