82443MX Datasheet, PDF (66/173 Pages) Intel Corporation – PCIset

82443MX PCIset
Transaction
REQa[4:0]# REQb[4:0]#
Support
Reserved
1 1 0 0 x 0 0 x x x Reserved
Memory Read &
Invalidate
00010
0 0 x LEN# Host initiated memory read cycles are forwarded to
DRAM or the PCI bus. An MRI cycle is initiated for a
PCI-initiated write cycle to DRAM.
Reserved
0 0 0 1 1 0 0 x LEN# Reserved
Memory Code Read 0 0 1 0 0
0 0 x LEN# Memory code read cycles are forwarded to DRAM or
PCI.
Memory Data Read 0 0 1 1 0
0 0 x LEN# Host initiated memory read cycles are forwarded to
DRAM or the PCI bus. A memory read cycle is initiated
for a PCI-initiated read cycle to DRAM.
Memory Write
(no retry)
00101
0 0 x LEN# This memory write is a writeback cycle and cannot be
retried. The write is forwarded to DRAM.
Memory Write
(can be retried)
00111
0 0 x LEN# The standard memory write cycle is forwarded to DRAM
or PCI.
Notes:
For Memory cycles, REQa[4:3]# = ASZ#. The 440MX only supports ASZ# = 00 (32-bit address).
REQb[4:3]# = DSZ#. For the mobile Celeron processor / Pentium II processor, DSZ# = 00 (64-bit data bus size).
LEN# = data transfer length as follows:
LEN# Data length
00
<= 8 bytes (BE[7:0]# specify granularity)
01
Length = 16 bytes BE[7:0]# all active (not supported)
10
Length = 32 bytes BE[7:0]# all active
11
Reserved
Table 37 shows the supported host bus responses.
Table 37. Host Bus Responses Supported
RS2# RS1# RS0#
Description
440MX Support
0
0
0
Idle
0
0
1
Retry Response
This response is generated if an access is made to a
resource that cannot be accessed by the processor at
that time and the logic must avoid deadlock. PCI-directed
reads, writes, and DRAM locked reads can be retried.
0
1
0
Deferred Response
This response can be returned for all transactions that
can be executed ‘out of order.’ PCI-directed reads
(memory, I/O and Interrupt Acknowledge) and writes (I/O
only) can be deferred.
0
1
1
Reserved
Reserved
1
0
0
Hard Failure
Not supported.
1
0
1
No Data Response
This response is for transactions where the data has
been transferred or for transactions where no data is
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