301467-005 Datasheet, PDF (89/426 Pages) Intel Corporation – Express Chipset

Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.26
TOLUD—Top of Low Usable DRAM (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
9Ch
08h
R/W
8 bits
This 8-bit register defines the Top of Low Usable DRAM. TSEG and Graphics Stolen Memory
(82915G only) are within the DRAM space defined. From the top, the (G)MCH optionally claims
1 to 32 MB of DRAM for internal graphics if enabled (82915G/82915GV/82915GL/82910GL
GMCH only), and 1, 2, or 8 MB of DRAM for TSEG if enabled. These bits are LT Lockable.
Bit Access &
Default
Description
7:3
R/W
Top of Low Usable DRAM (TOLUD): This register contains bits 31:27 of an
01h
address one byte above the maximum DRAM memory that is usable by the
operating system. Address bits 31:27 programmed to 01h implies a minimum
memory size of 128 MBs.
Configuration software must set this value to the smaller of the following 2 choices:
• Maximum amount memory in the system plus one byte or the minimum address
allocated for PCI memory.
Address bits 26:0 are assumed to be 000_0000h for the purposes of address
comparison. The host interface positively decodes an address towards DRAM if the
incoming address is less than the value programmed in this register.
If this register is set to 0000 0b, it implies 128 MBs of system memory.
Note: The Top of Low Usable DRAM is the lowest address above both Graphics
Stolen memory (82915G/82915GV/82915GL/82910GL only) and TSEG. The host
interface determines the base of Graphics Stolen Memory by subtracting the
Graphics Stolen Memory Size from TOLUD and further decrements by 1 MB to
determine base of TSEG.
2:0
Reserved
Programming Example (82915G/82915GV/82915GL/82910GL GMCH only):
• C1DRB7 is set to 4 GB
• TSEG is enabled and TSEG size is set to 1 MB
• Internal Graphics is enabled and Graphics Mode Select is set to 32 MB
• BIOS knows the OS requires 1G of PCI space.
BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the system. This
20-MB range at the very top of addressable memory space is lost to APIC.
According to the above equation, TOLUD is originally calculated to: 4 GB = 1_0000_0000h
The system memory requirements are:
4 GB (max addressable space) – 1 GB (PCI space) – 20 MB (lost memory) =
3 GB – 128 MB (minimum granularity) = B800_0000h
Since B800_0000h (PCI and other system requirements) is less than 1_0000_0000h, TOLUD
should be programmed to B8h.
Datasheet
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