301467-005 Datasheet, PDF (399/426 Pages) Intel Corporation – Express Chipset

Testability
R
15 Testability
In the (G)MCH, testability for Automated Test Equipment (ATE) board level testing has been
implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin
connected to it.
15.1 Complimentary Pins
Table 15-1 contains pins which must remain complimentary while performing XOR testing. The
first and third columns contain the pin and its compliment. The second and fourth columns
specify which chain the associated pins are on.
Note: The SDQSx# pins are only used in DDR2 mode. In DDR it is not necessary to drive
SDQS_A[7:0]# or SDQS_B[7:0]#.
Table 15-1. Complimentary Pins to Drive
Complimentary Pin
XOR Chain
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
SDQS_A0
SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SDQS_A8
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SDQS_B8
FSB XOR 1
FSB XOR 0
FSB XOR 0
FSB XOR 0
SM XOR 6
SM XOR 6
SM XOR 6
SM XOR 4
SM XOR 4
SM XOR 2
SM XOR 2
SM XOR 2
SM XOR 2
SM XOR 7
SM XOR 7
SM XOR 7
SM XOR 7
SM XOR 7
SM XOR 3
SM XOR 3
SM XOR 3
SM XOR 7
Complimentary Pin
H_DSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
SDQS_A0#
SDQS_A1#
SDQS_A2#
SDQS_A3#
SDQS_A4
SDQS_A5#
SDQS_A6#
SDQS_A7#
SDQS_A8#
SDQS_B0#
SDQS_B1#
SDQS_B2#
SDQS_B3#
SDQS_B4#
SDQS_B5#
SDQS_B6#
SDQS_B7#
SDQS_B8#
XOR Chain
FSB XOR 1
FSB XOR 0
FSB XOR 0
FSB XOR 0
SM XOR 4
SM XOR 4
SM XOR 4
SM XOR 6
SM XOR 2
SM XOR 4
SM XOR 4
SM XOR 4
SM XOR 4
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
Datasheet
399