301467-005 Datasheet, PDF (217/426 Pages) Intel Corporation – Express Chipset

System Address Map
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11.4.1
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed
SMM space is defined as the range of bus addresses used by the processor to access SMM space.
DRAM SMM space is defined as the range of physical DRAM memory locations containing the
SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible,
High, and TSEG. The Compatible and TSEG SMM space is not remapped; therefore, the
addressed and DRAM SMM space is the same address range. Since the High SMM space is
remapped, the addressed and DRAM SMM space are different address ranges. Note that the High
DRAM space is the same as the Compatible Transaction Address space. The following table
describes three unique address ranges:
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
SMM Space Enabled
Compatible (C)
High (H)
TSEG (T)
Transaction Address Space
000A_0000h to 000B_FFFFh
FEDA_0000h to FEDB_FFFFh
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
DRAM Space (DRAM)
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
11.4.2
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are unpredictable and
may cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• High or TSEG SMM transaction address space must not overlap address space assigned to
system main memory, or to any “PCI” devices (including DMI, PCI Express, and graphics
devices). This is a BIOS responsibility.
• Both D_OPEN and D_CLOSE capability must not be enabled at the same time.
• When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as
available main memory. This is a BIOS responsibility.
• Any address translated through the internal graphics device’s TLB must not target main
memory from A_0000-F_FFFF.
Datasheet
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