301467-005 Datasheet, PDF (69/426 Pages) Intel Corporation – Express Chipset

Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.3
PCICMD—PCI Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
04h
0006h
RO, R/W
16 bits
Since (G)MCH Device 0 does not physically reside on Primary PCI bus, many of the bits are not
implemented.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Access &
Default
RO
0b
R/W
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
1b
RO
1b
RO
0b
Description
Reserved
Fast Back-to-Back Enable (FB2B). This bit controls whether or not the master
can do fast back-to-back write. Since device 0 is strictly a target this bit is not
implemented and is hardwired to 0.
SERR Enable (SERRE). This bit is a global enable bit for Device 0 SERR
messaging. The (G)MCH does not have a SERR signal. The (G)MCH
communicates the SERR condition by sending an SERR message over DMI to
the ICH6.
1 = Enable. The (G)MCH is enabled to generate SERR messages over DMI for
specific Device 0 error conditions that are individually enabled in the
ERRCMD register. The error status is reported in the ERRSTS, and PCISTS
registers. If SERRE is clear, then the SERR message is not generated by the
(G)MCH for Device 0.
0 = Disable
Note: That this bit only controls SERR messaging for the Device 0. Device 1 has
its own SERRE bits to control error reporting for error conditions occurring in that
device. The control bits are used in a logical OR manner to enable the SERR
DMI message mechanism.
Address/Data Stepping Enable (ADSTEP). Hardwired to 0.
Parity Error Enable (PERRE). PERR# is not implemented by the (G)MCH and
this bit is hardwired to 0.
VGA Palette Snoop Enable (VGASNOOP). Hardwired to a 0.
Memory Write and Invalidate Enable (MWIE). The (G)MCH will never issue
memory write and invalidate commands. This bit is therefore hardwired to 0.
Reserved
Bus Master Enable (BME). The (G)MCH is always enabled as a master. This bit
is hardwired to a "1".
Memory Access Enable (MAE). The (G)MCH always allows access to main
memory. This bit is not implemented and is hardwired to 1.
I/O Access Enable (IOAE). Hardwired to a 0.
Datasheet
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