301467-005 Datasheet, PDF (214/426 Pages) Intel Corporation – Express Chipset

System Address Map
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11.3.1
11.3.2
11.3.3
11.3.4
APIC Configuration Space (FEC0_0000h-FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the ICH6
portion of the chipset, but may also exist as stand-alone components.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be
populated in the system. Since it is difficult to relocate an interrupt controller using plug-and-play
software, fixed address decode regions have been allocated for them. Processor accesses to the
default IOAPIC region (FEC0_0000h to FEC7_FFFFh) are always forwarded to DMI.
HSEG (FEDA_0000h–FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window to
SMM memory. It is sometimes called the High SMM memory space. SMM-mode processor
accesses to the optionally enabled HSEG are remapped to 000A_0000h – 000B_FFFFh. Non-
SMM-mode processor accesses to enabled HSEG are considered invalid and are terminated
immediately on the FSB. The exceptions to this rule are Non-SMM-mode write-back cycles that
are remapped to SMM space to maintain cache coherency. PCI Express and DMI originated
cycles to enabled SMM space are not allowed. Physical main memory behind the HSEG
transaction address is not remapped and is not accessible. All cacheline writes with WB attribute
or Implicit write backs to the HSEG range are completed to DRAM like an SMM cycle.
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any device on PCI
Express or DMI may issue a memory write to 0FEEx_xxxxh. The (G)MCH will forward this
memory write along with the data to the FSB as an Interrupt Message Transaction. The (G)MCH
terminates the FSB transaction by providing the response and asserting HTRDY#. This memory
write cycle does not go to DRAM.
High BIOS Area
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI memory address range is reserved for
system BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system
BIOS. The processor begins execution from the High BIOS after reset. This region is mapped to
the DMI so that the upper subset of this region aliases to the 16-MB–256-KB range. The actual
address space required for the BIOS is less than 2 MB, but the minimum processor MTRR range
for this region is 2 MB; thus, that full 2 MB must be considered.
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Datasheet