301467-005 Datasheet, PDF (47/426 Pages) Intel Corporation – Express Chipset

Signal Description
R
Interface
Signal Name
Host I/F
HHIT#
HHITM#
HLOCK#
HREQ[4:0]#
HTRDY#
HRS[2:0]#
HBREQ0#
HPCREQ#
HVREF
HRCOMP
State During
I/O
RSTIN#
Assertion
I/O
TERM HV
I/O
TERM HV
I/O
TERM HV
I/O
TERM HV
O
TERM HV
O
TERM HV
I/O
TERM HV
I
TERM HV
I
IN
I/O
TRI
State After
RSTIN# De-
assertion
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
IN
TRI after RCOMP
HSWING
I
IN
IN
HSCOMP
I/O
TRI
TRI
Table 2-2. System Memory (DDR2) Reset and S3 States
Interface
Signal Name
System
Memory
(DDR2)
Channel A
SCLK_A[5:0]
SCLK_A[5:0]#
SCS_A[3:0]#
SMA_A[13:0]
SBS_A[2:0]
SRAS_A#
SCAS_A#
SWE_A#
SDQ_A[63:0]
SDM_A[7:0]
SDQS_A[7:0]
SDQS_A[7:0]#
SCKE_A[3:0]
SODT_A[3:0]
State During
I/O
RSTIN#
Assertion
O
TRI
O
TRI
O
TRI
O
TRI
O
TRI
O
TRI
O
TRI
O
TRI
I/O
TRI
O
TRI
I/O
TRI
I/O
TRI
O
LV
O
LV
State After
RSTIN# De-
assertion
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
LV
LV
S3
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI
TRI
TRI
S3
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
LV
LV
Pull-up/
Pull-down
20 Ω resistor
for board with
target
impedance of
60 Ω
Pull-up/
Pull-down
Datasheet
47