301467-005 Datasheet, PDF (219/426 Pages) Intel Corporation – Express Chipset

System Address Map
R
11.4.5
11.4.6
11.4.7
11.4.8
SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI originated
transactions are not allowed to SMM space.
Processor WB Transaction to an Enabled SMM Address
Space
Processor write-back transactions (HREQ1# = 0) to enabled SMM address space must be written
to the associated SMM DRAM, even though the space is not open and the transaction is not
performed in SMM mode. This ensures SMM space cache coherency when cacheable extended
SMM space is used.
SMM Access through GTT TLB (Intel^®
82915G/82915GV/82910GL GMCH Only)
Accesses through GTT TLB address translation to enabled SMM DRAM space are not allowed.
Writes will be routed to memory address 0h with byte enables de-asserted and reads will be
routed to memory address 0h. If a GTT TLB translated address hits enabled SMM DRAM space,
an Invalid Translation Table Entry Flag is reported to BIOS.
PCI Express and DMI originated accesses are never allowed to access SMM space directly or
through the GTT TLB address translation. If a GTT TLB translated address hits enabled SMM
DRAM space, an Invalid Translation Table Entry Flag is reported to BIOS.
PCI Express and DMI write accesses through graphics memory range set up by BIOS will be
snooped. If, when translated, the resulting physical address is to enabled SMM DRAM space, the
request will be remapped to address 0h with de-asserted byte enables.
PCI Express and DMI read accesses to the graphics memory range set up by BIOS are not
supported; therefore, users/systems will have no address translation concerns. PCI Express and
DMI reads to the graphics memory range will be remapped to address 0h. The read will complete
with UR (unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure they are not in SMM (actually, anything
above base of TSEG or 640 KB – 1 MB). Thus, they will be invalid and go to address 0h. This is
not specific to PCI Express or DMI; it applies to the processor or internal graphics engines. Also,
since the graphics memory range snoop would not be directly to SMM space, there would not be
a writeback to SMM. In fact, the writeback would also be invalid (because it uses the same
translation) and goes to address 0h.
Memory Shadowing
Any block of memory that can be designated as “read only” or “write only” can be “shadowed”
into (G)MCH main memory. Typically, this is done to allow ROM code to execute more rapidly
out of main DRAM memory. ROM is used as read-only during the copy process while DRAM at
the same time is designated write-only. After copying, the DRAM is designated read-only so that
ROM is shadowed. Processor bus transactions are routed accordingly.
Datasheet
219